Multi-Core Processor NoC Architecture for RTM Power Efficiency
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Solution Overview
Problem
High-performance computing systems, particularly those used in seismic image processing via Reverse Time Migration (RTM), face significant power consumption challenges, limiting their efficiency and performance due to the extensive resources required to process seismic survey data.
Innovation Solution
A scalable multiple-core processor architecture with Network-on-Chip (NoC) inter-processor communication and energy-efficient design, featuring Tensilica LX2 cores, software-controlled memory, and automatic cache management, optimized for parallel computing applications from embedded devices to cloud computing, including support for Reverse Time Migration (RTM) processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If conventional high-performance computing systems are used for Reverse Time Migration processing, then computational capability is sufficient, but power consumption becomes excessive (many megawatts)
Solution Approach 1:
The system is divided into multiple independent processor cores (e.g., 128 cores) that can operate in parallel. Each core handles a portion of the RTM computational workload, allowing the system to achieve high computational capability while distributing power consumption across multiple smaller units rather than concentrating it in a single high-power processor.
Solution Approach 2:
The patent transitions from a single-processor architecture to a multi-core parallel architecture, adding the dimension of parallelism. This dimensional change allows the system to perform computations simultaneously across multiple cores, achieving the required computational capability for RTM while maintaining lower power consumption per core compared to a single high-performance processor.
2Productivity
If more computational resources are allocated to RTM processing, then processing speed increases, but power consumption increases proportionally
Solution Approach 1:
The multi-core architecture enables continuous processing of RTM workloads by distributing tasks across multiple cores that can operate simultaneously and continuously. This parallel continuous operation achieves high processing speed while maintaining efficient power utilization compared to sequential processing on a single high-power processor.
Solution Approach 2:
The system changes the architectural parameter from a single high-power processor to multiple lower-power processors operating in parallel. This parameter change allows the system to achieve equivalent or superior processing speed through parallelism while reducing overall power consumption, as each core operates at a lower power level than a single high-performance processor would require.
3Device complexity
If a single high-performance processor is used, then system complexity is low, but power consumption is excessive
Solution Approach 1:
The system segments the processing function into multiple independent cores, each with its own memory and cache resources. While this increases the number of components, it reduces the power consumption of each individual unit, and the overall system achieves better power efficiency despite the increased component count.
Solution Approach 2:
Each processor core is designed as a universal computing unit that can handle various RTM computational tasks. This multi-functionality allows the same core architecture to be replicated across multiple units, achieving the required computational capability through parallelism rather than through a single specialized high-power processor, thereby reducing overall power consumption.
Data Source
AI summary
A multi-core computer processor including a plurality of processor cores interconnected in a Network-on-Chip (NoC) architecture, a plurality of caches, each of the plurality of caches being associated with one and only one of the plurality of processor cores, and a plurality of memories, each of the plurality of memories being associated with a different set of at least one of the plurality of processor cores and each of the plurality of memories being configured to be visible in a global memory address space such that the plurality of memories are visible to two or more of the plurality of processor cores, wherein at least one of a number of the processor cores, a size of each of the plurality of caches, or a size of each of the plurality of memories is configured for performing a reverse-time-migration (RTM) computation.