Multi-Core Packet Classification via Decision Tree Partitioning
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing packet classification methods for firewalls and security gateways are inefficient on multi-core processors due to redundant classifier data structures not considering memory hierarchy and processor architecture, leading to performance bottlenecks.
Innovation Solution
A method for multi-core processor-based packet classification that constructs a decision tree data structure by recursively partitioning the search space to reduce the number of rules in each subspace, selecting partition fields and points to minimize rules in sub-spaces, and using a first-in-first-out queue to process elements, ensuring efficient classification.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a decision tree data structure is constructed without considering memory hierarchy and processor architecture, then the classifier data structure can be built, but the performance on multi-core processors deteriorates due to redundancy and inefficiency
Solution Approach 1:
The patent divides the packet classification task into multiple independent threads, each handling a specific subset of classification rules. This segmentation allows parallel processing on multi-core processors while reducing the complexity of individual thread execution, directly addressing the performance deterioration issue.
Solution Approach 2:
The patent introduces a new dimension to the decision tree structure by adding thread ID and rule range dimensions. This transforms the traditional single-thread decision tree into a multi-dimensional structure that can be efficiently distributed across multiple processors, eliminating redundancy and improving performance.
2Productivity
If specialized hardware solutions like ASIC/FPGA are used, then high-performance packet classification is achieved, but the time-to-market increases and cost increases
Solution Approach 1:
The patent creates a software-based packet classification system that copies and emulates the functionality of specialized hardware like ASIC/FPGA using general-purpose processors. This software implementation achieves comparable performance while avoiding the long development cycles and high costs of hardware customization, thus reducing time-to-market.
Solution Approach 2:
The patent replaces specialized hardware mechanisms with software-based multi-core processor mechanisms. By using general-purpose processors with parallel programming capabilities, the system achieves high-performance packet classification without the constraints of hardware design cycles, thereby reducing time-to-market and cost.
3Device complexity
If a traditional decision tree data structure is used without considering processor architecture, then the classification logic is simple, but the scalability to multi-core processors deteriorates
Solution Approach 1:
The patent transforms the static decision tree data structure into a dynamic, flexible structure that can adapt to multi-core processor architectures. The structure includes configurable parameters such as thread count, rule distribution strategies, and memory management policies, allowing it to dynamically adjust to different hardware configurations while maintaining manageable complexity.
Data Source
AI summary
The present invention relates to a method for multi-core processor based packet classification on multiple fields. The invention specifically proposes three methods to select partition points, two associated methods to select dimensions, then receiving packet information after the data structure of classification is constructed, and searching the data structure of classification according to packet information to get matched results. The present invention can be implemented on many types of multi-core processor based platforms which ensure favorable performance and adaptive capabilities for different network applications, and significantly reduce the product cost of high-end routers and firewalls.