Multi-Core Packet Processing for High-Speed Data Flows
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Solution Overview
Problem
The processing speed of data in electronic devices is insufficient to handle increasing data amounts and transmission/reception speeds, leading to delayed information retrieval and user discomfort.
Innovation Solution
A multi-core processor is employed in electronic communication devices, utilizing a control core to manage data distribution among operation cores for efficient packet merging and processing, including a packet merging unit that selectively performs GRO operations based on attribute-based data allocation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If packet merging function is performed in software, then data processing efficiency is improved, but processor load increases and processing speed becomes insufficient
Solution Approach 1:
The processor is divided into multiple operation cores, each independently performing packet merging operations on allocated data flows. This segmentation distributes the processing load across multiple cores, preventing any single core from becoming a bottleneck while maintaining high processing efficiency through parallel operation.
Solution Approach 2:
The patent transitions from single-core sequential processing to multi-core parallel processing, adding a dimensional aspect to the data processing architecture. By allocating different data flows to different operation cores simultaneously, the system achieves higher throughput without proportionally increasing processor complexity.
2Speed
If more data is processed at higher speed, then communication capability is improved, but processing speed becomes the limiting factor
Solution Approach 1:
The control core performs preliminary actions by classifying and allocating data flows to appropriate operation cores before the actual packet merging processing begins. This pre-organization of data ensures that operation cores can immediately begin processing without waiting or contention, maximizing the utilization of processing speed for actual data transformation rather than coordination overhead.
Solution Approach 2:
Each operation core independently processes its allocated data flow without requiring continuous intervention from the control core. The operation cores autonomously perform packet merging on their respective data flows, enabling self-service processing that scales efficiently with increasing data volumes and transmission speeds.
3Productivity
If packet merging is performed on all data flows, then processing efficiency is improved, but processor load becomes excessive
Solution Approach 1:
The control core applies different processing qualities to different data flows based on their characteristics. By classifying data flows and selectively allocating them to operation cores for packet merging, the system applies packet merging processing locally where it provides the most benefit, rather than uniformly to all data flows. This selective approach maintains high processing efficiency for suitable data while conserving processor load for other tasks.
Data Source
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AI summary
An electronic device including a communication circuit receiving data transmitted from another electronic device, a memory storing instructions, and at least one processor electrically connected to the communication circuit and the memory and including a control core and a plurality of operation cores. The at least one processor may execute the stored instructions to cause the control core to receive the data from the communication circuit, to classify the received data into data flows of a specified number depending on an attribute of the data, and to respectively allocate the data flows to the plurality of operation cores.