Multi-Core Data Transmission Circuit for Selective Packet Relay

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Solution Overview

Problem

Existing data transmission methods in multi-core chips result in high power consumption, data blocking, and reduced utilization rates due to unnecessary data processing and storage across all cores, leading to inefficient data transmission and processing.

Innovation Solution

A data transmission circuit with a receiving unit, controlling unit, lookup table unit, and selecting unit that allows parallel storage and relay of data packets, reducing power consumption by analyzing control bits in the header and enabling selective transmission based on destination cores, thereby optimizing data routing.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If broadcast transmission is used to send data from one core to multiple cores, then all target cores can receive the data, but power consumption increases and data blocking occurs

Engineering Contradiction:
Improvedata delivery completenessVSAvoidpower consumption
Core Design Contradiction:
ReliabilityVSUse of energy by moving object

Solution Approach 1:

The patent extracts the header information (control bits, destination addresses) from the data packet and processes it separately in the controlling unit. This allows the system to determine which cores need the data without broadcasting the entire packet to all cores, thereby reducing power consumption while ensuring complete data delivery to intended recipients.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The data transmission process is segmented into header analysis and data forwarding stages. The controlling unit analyzes control bits and destination addresses separately from the actual data payload, enabling selective forwarding to specific cores rather than universal broadcasting, thus reducing unnecessary power consumption.

Inventive Principle:
Principle #1Segmentation

2Reliability

If broadcast transmission is used to send data from one core to multiple cores, then all target cores can receive the data, but data blocking and reduced Fabric utilization occur

Engineering Contradiction:
Improvedata delivery completenessVSAvoidFabric utilization rate
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent extracts destination address information from the header and uses it to selectively forward data packets through the Fabric only to intended target cores. This prevents unnecessary occupancy of the Fabric by broadcast traffic, reducing data blocking and improving overall Fabric utilization and system productivity.

Inventive Principle:
Principle #2Taking out (Extraction)

3Adaptability or versatility

If intermediate relay core stores data in local storage region before relaying, then data can be forwarded to multiple cores, but access to local storage region is affected and power consumption increases

Engineering Contradiction:
Improvedata relay capabilityVSAvoidpower consumption
Core Design Contradiction:
Adaptability or versatilityVSUse of energy by moving object

Solution Approach 1:

The patent performs preliminary action by analyzing the control bits and destination addresses in the header before the data packet reaches the local storage region. This early analysis enables selective forwarding decisions to be made upfront, allowing data to be relayed directly without unnecessary storage operations, thereby reducing power consumption while maintaining relay capability.

Inventive Principle:
Principle #10Preliminary action

4Reliability

If all cores receive and process the data packet, then data can be delivered to multiple cores, but unnecessary processing increases burden and power consumption

Engineering Contradiction:
Improvedata delivery completenessVSAvoidenergy waste
Core Design Contradiction:
ReliabilityVSLoss of energy

Solution Approach 1:

The patent extracts destination address information from the header and uses it to filter and forward data packets only to intended target cores. This prevents unnecessary cores from receiving and processing the data, eliminating energy waste associated with unwanted data processing while ensuring complete and accurate data delivery to the correct recipients.

Inventive Principle:
Principle #2Taking out (Extraction)

Data Source

PatentEP3989077B1Data transmission circuit and method, core, chip, electronic device, and storage medium
Publication Date: 2025.12.17 STREAM COMPUTING INC
  • EP3989077B1 patent drawingFigure 1~2
  • EP3989077B1 patent drawingFigure 3~4
  • EP3989077B1 patent drawingFigure 5~7

AI summary

The present disclosure provides a data transmission circuit and method, a core, a chip with a multi-core structure, an electronic device and a storage medium. The data transmission circuit includes a receiving unit, a controlling unit, a lookup table unit and a selecting unit. The receiving unit is for receiving an original data packet from Fabric; the controlling unit is for determining whether the original data packet needs to be relayed according to an original control bit, and for controlling a first input terminal of the selecting unit to be enabled in response to that the original data packet needs to be relayed; the selecting unit is for sending a new data packet to the Fabric via the first input terminal, wherein the new data packet includes the original data and a new header acquired by the lookup table unit according to an original index. In this way, power consumption of the data transmission circuit is effectively reduced.