Multicore Page Fault Processing via Core Segmentation
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Solution Overview
Problem
Processors face difficulties in implementing restartable page faults due to the need to suspend and restart multiple instructions during vector operations, which requires holding large transient data and increases memory usage, especially in vector gather/scatter instructions where page fault detection is delayed.
Innovation Solution
An information processing device with a first processor core and a second processor core, where the second core stops new instruction issuance and notifies the first core upon detecting a page fault, allowing the first core to judge permissibility and update the page table, enabling the second core to restart instructions in a transient state.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the processor executes multiple instructions ahead of time to increase execution efficiency, then productivity is improved, but the number of inflight instructions increases which requires holding larger transient information
Solution Approach 1:
The patent segments the processor into two distinct cores: a first processor core that handles control and management functions including page fault processing, and a second processor core that executes parallel operation processing including vector instructions. This segmentation allows the second core to maintain a large number of inflight instructions for high productivity while the first core manages the complexity of page fault handling, thereby resolving the contradiction between execution efficiency and transient information storage requirements
Solution Approach 2:
The first processor core acts as an intermediary between the operating system and the second processor core. It receives page fault notifications from the second core, processes the faults by updating the page table, and manages the restart of instructions. This intermediary role allows the second core to focus on executing multiple instructions ahead of time without being burdened by the complexity of page fault handling, thus maintaining high execution efficiency while managing transient information requirements
2Reliability
If the processor implements restartable page fault by suspending execution to determine page fault occurrence, then reliability is improved, but the execution efficiency deteriorates due to instruction suspension
Solution Approach 1:
The patent implements a dynamic page fault handling mechanism where the second processor core can suspend execution upon detecting a page fault and later restart instructions after the first core processes the fault. The system dynamically adjusts between continuous execution and suspended execution based on page fault conditions, allowing reliable page fault handling while minimizing impact on overall execution efficiency through quick restart capability
Solution Approach 2:
The system employs a feedback mechanism where the second processor core notifies the first core when a page fault occurs, and after the first core updates the page table and determines the fault is permissible, it sends a restart direction back to the second core. This feedback loop ensures reliable page fault handling while maintaining execution efficiency by quickly resuming instruction execution after fault resolution
3Reliability
If the processor holds transient information of large size to execute instructions in a cancellable state, then restartable page fault is achieved, but memory usage increases
Solution Approach 1:
By segmenting the processor into two cores with distinct responsibilities, the patent reduces the memory burden on the second core. The first core handles page fault processing and page table updates, allowing the second core to hold only essential transient information needed for instruction restart rather than large amounts of data, thus achieving restartable page fault with reduced memory usage
Solution Approach 2:
The patent uses a page table copying mechanism where the first processor core updates the page table in response to page faults. This allows the second core to restart instructions without needing to hold large amounts of transient information, as the updated page table provides the necessary memory mapping information for resuming execution, thereby reducing memory usage while maintaining restart capability
Data Source
AI summary
A first processor core with an operating system installed and a second processor core controlled by the first processor core and capable of executing parallel operation processing are included. The second processor core, when detecting a page fault, stops new instruction issue and stops as an issued and uncompleted instruction can be restarted, and also sends notification of page fault detection to the first processor core. The first processor core includes a permissibility judgment part that judges whether or not the page fault is permissible in response to reception of the notification, a page table updating part that updates a page table included by the second processor core in accordance with a result of the judgment by the permissibility judgment part, and a directing part that sends a direction corresponding to a result of the judgment by the permissibility judgment part to the second processor core.