Multi-Core Performance Verification Device for Vehicle Control Systems
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Solution Overview
Problem
Conventional techniques lack the ability to perform PIL simulation for programs executed on multi-core microcomputers, as they are incompatible with the simulation speed required for design, and fail to divide code generated by a controller model into multiple CPU cores while considering communication overhead, making it impossible to detect transient states within a predetermined cycle in vehicle control systems with short control cycles.
Innovation Solution
A performance verification device that selects a code generation range for a multi-core processor, designates parallel executable units, associates them with cores, and generates source code for execution, allowing for cooperative simulation with a plant model to measure execution time and improve control speed by determining actuator control during previous cycles.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional PIL simulation techniques are used for single-core processors, then simulation compatibility is maintained, but the ability to verify multi-core processor performance is lost
Solution Approach 1:
The control program is divided into multiple tasks that can be executed in parallel on different CPU cores. The simulation system segments the verification process to handle multi-core execution patterns, allowing each core's task to be simulated independently while maintaining overall system accuracy.
Solution Approach 2:
The performance verification device is designed to universally handle both single-core and multi-core processor simulations. It can adapt its simulation methodology to match the target processor architecture, providing reliable verification across different processor types without requiring separate specialized tools.
2Productivity
If code is divided into parallel executable units for multi-core processing, then processing speed is improved, but communication overhead between cores increases
Solution Approach 1:
The simulation measures and accounts for communication overhead between CPU cores in advance, before actual deployment. By pre-characterizing the communication costs between different core pairs, the system can optimize task allocation to minimize overhead while maintaining parallel processing speedups.
Solution Approach 2:
The performance verification device acts as an intermediary that models and predicts communication overhead between cores. It provides a simulation environment where communication costs can be measured and optimized without incurring actual hardware overhead, allowing designers to minimize communication penalties before deployment.
3Speed
If simulation speed is increased to meet design requirements, then detection of transient states is improved, but measurement precision of execution time deteriorates
Solution Approach 1:
The system performs preliminary simulation at high speed to identify transient states and performance bottlenecks. Once critical issues are identified through fast simulation, targeted detailed measurements are performed on specific code segments to obtain precise execution time data without sacrificing overall simulation throughput.
Solution Approach 2:
Instead of measuring every execution time at full precision throughout the entire simulation, the system applies partial precision measurement only to critical paths and transient states that affect overall performance. This selective measurement approach maintains simulation speed while obtaining sufficient precision for decision-making.
Data Source
AI summary
When generating a source code executed by a multi-core processor in order to verify performance of a control system, a device generates the source code as an object of execution by the multi-core processor from a control model, performs cooperative simulation, and measures an execution time of a program in the multi-core processor in the cooperative simulation.