Multi-Core PLC Control for Periodic and Non-Periodic Tasks

Solution Overview

Problem

Conventional programmable logic controllers (PLCs) face challenges in executing high-speed, high-precision periodic processes while also handling non-periodic processes like informatization, leading to performance issues and resource interference.

Innovation Solution

A control device with a multi-core processor architecture, where high-speed, high-precision processes are assigned to specific cores and non-periodic applications like informatization processes are executed on a separate core, allowing efficient resource allocation and minimizing interference.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If a single processor executes both high-speed periodic control processes and non-periodic informatization processes, then device complexity is reduced, but the high-speed control precision and timing are degraded due to resource interference

Engineering Contradiction:

Improveprocessor architectureVSAvoidcontrol precision

Core Design Contradiction:

Device complexityVSMeasurement precision

Solution Approach 1:

The processor is segmented into multiple independent cores: a first processor core dedicated to executing periodic control programs for high-speed control, and a second processor core dedicated to executing non-periodic applications for informatization. This segmentation eliminates resource interference between different process types while maintaining device complexity at an acceptable level through integrated multi-core architecture.

Inventive Principle:

Principle #1Segmentation

2Volume of stationary object

If a single processor executes both high-speed periodic control processes and non-periodic informatization processes, then device size is reduced, but the execution speed and responsiveness are degraded due to resource contention

Engineering Contradiction:

Improvedevice sizeVSAvoidexecution speed

Core Design Contradiction:

Volume of stationary objectVSSpeed

Solution Approach 1:

The processor is segmented into multiple independent cores: a first processor core dedicated to executing periodic control programs for high-speed control, and a second processor core dedicated to executing non-periodic applications for informatization. This segmentation eliminates resource interference between different process types while maintaining device complexity at an acceptable level through integrated multi-core architecture.

Inventive Principle:

Principle #1Segmentation

3Productivity

If multiple processors are used to separate high-speed control processes and non-periodic informatization processes, then control precision and execution speed are improved, but device complexity and size increase

Engineering Contradiction:

Improveexecution speedVSAvoidprocessor architecture

Core Design Contradiction:

ProductivityVSDevice complexity

Solution Approach 1:

Multiple processor cores are merged into a single integrated processor unit, allowing simultaneous execution of periodic control programs on the first core and non-periodic applications on the second core. This merging achieves the functional separation benefits of multiple processors while maintaining a compact, unified device structure that does not significantly increase overall complexity or size.

Inventive Principle:

Principle #5Merging (Combining)

Data Source

PatentEP3582036B9Control device

Publication Date: 2023.08.23 OMRON CORP

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Figure 3(A)~3(E)

AI summary

The purpose of the present invention is to achieve miniaturization, higher performance, and informatization with regard to a control device. The fourth core (114) of a PLC (10) has allocated thereto only applications which do not need to be executed repeatedly at execution intervals that are less than or equal to a prescribed time interval with regard to a control subject.