Multicore Non-Volatile Process Persistence for Power Recovery
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Solution Overview
Problem
Existing persistence mechanisms in computing systems are limited in making systems fully non-volatile and introduce significant overhead, with methods like hibernation and checkpoint-restarts being inefficient and incomplete, leading to system failures and latency issues during power failures.
Innovation Solution
A method and computing device utilizing a non-volatile memory and multiple cores to perform a stop procedure during power failure, including scheduling processes, stopping devices, and storing context information, followed by a go procedure upon power recovery to ensure persistence and efficient system restart.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If hibernation is used to provide persistence during power failure, then system recovery is possible, but the entire system image must be serialized which requires external power sources and cannot succeed without them
Solution Approach 1:
The patent extracts only the essential process states and context information needed for recovery, storing them in non-volatile memory, rather than serializing the entire system image as required by traditional hibernation. This selective extraction eliminates the need for external power sources during the persistence operation.
Solution Approach 2:
The patent performs preliminary actions by proactively saving process control blocks and device states to non-volatile memory before power failure occurs, using the persistent storage capability inherent in modern storage systems. This preliminary persistence action ensures recovery can proceed without external power assistance.
2Reliability
If checkpoint-restarts are used to provide persistence, then system recovery is possible, but serious system overhead is introduced due to redundant data dumps
Solution Approach 1:
The patent extracts and stores only the minimal necessary state information (process control blocks and device states) in non-volatile memory, eliminating the redundant data dumps characteristic of checkpoint-restart mechanisms. This selective persistence approach dramatically reduces the time overhead while maintaining recovery capability.
3Reliability
If checkpoint-restarts are used to provide persistence, then system recovery is possible, but the kernel must be rebooted which introduces extra latency to detect the exact resumption point
Solution Approach 1:
The patent performs preliminary actions by saving the exact execution context (process control blocks with program counters, device states) to non-volatile memory before power failure. This allows the system to resume execution precisely where it left off without requiring a full kernel reboot, eliminating the latency associated with detecting resumption points after reboot.
4Reliability
If existing persistence mechanisms are used to make the system non-volatile, then persistence is provided, but significant overhead is introduced
Solution Approach 1:
The patent extracts only the essential runtime state information (process control blocks and device states) and stores it in non-volatile memory, rather than making the entire system image non-volatile through traditional mechanisms. This selective approach provides the necessary persistence while minimizing runtime overhead by avoiding the serialization and management of unnecessary data.
Data Source
AI summary
A processor of the computing device includes a plurality of cores and executes one or more instructions stored in a memory module including a non-volatile memory, thereby performing a stop procedure upon a power failure and performing a go procedure upon power recovery. In the stop procedure, the processor accesses process control blocks of processes being run, scheduling each process to a run queue of a corresponding first core among first cores included in the cores, removes the scheduled process from the run queue and makes the removed process wait in a waiting queue, executes an idle task, and stops a device included in the computing device.