Multicore Dissimilar Processor Lanes for Common-Mode Fault Detection
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Solution Overview
Problem
Safety critical control systems face challenges in achieving similar safety and integrity levels when using dissimilar processor cores on separate system-on-chip devices, which complicates redundancy and fault detection in applications like aircraft controls and nuclear shutdown systems.
Innovation Solution
Implementing dissimilar processor cores for command and monitor lanes within a single system-on-chip device, utilizing a multicore processor architecture to enhance design diversity and ensure matching or mismatching outputs for fault detection, with alert signals for failure scenarios.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If dissimilar processor cores are implemented on separate system-on-chip devices, then design diversity between lanes is achieved to mitigate common mode faults, but it becomes difficult to obtain similar safety or integrity levels to both lanes
Solution Approach 1:
The patent merges previously separate system-on-chip devices into a single multicore processor device that contains both dissimilar processor cores. This integration maintains the design diversity between command and monitor lanes while ensuring both cores operate under identical safety constraints and fabrication processes, thereby achieving similar safety and integrity levels without the complexity of managing multiple separate devices
Solution Approach 2:
The multicore processor device serves multiple functions: it houses dissimilar processor cores for design diversity, provides identical safety constraints for both cores, and enables both command and monitor lane operations within a single universal platform. This multi-functionality resolves the contradiction by making one device perform what previously required multiple specialized devices
2Reliability
If separate system-on-chip devices are used for command and monitor lanes, then design diversity is achieved, but size, weight, area, power, and cost increase
Solution Approach 1:
The patent combines multiple separate system-on-chip devices into a single integrated multicore processor device. This merging reduces the overall physical footprint, weight, and area while maintaining the design diversity between dissimilar processor cores that enables fault detection capability in both command and monitor lanes
3Reliability
If separate system-on-chip devices are used for each lane, then design diversity is achieved, but power consumption increases
Solution Approach 1:
The patent merges separate system-on-chip devices into a single multicore processor device, reducing the number of independent power supplies and interconnections required. This integration lowers overall power consumption while maintaining the safety critical operations through dissimilar processor cores that provide redundant fault detection capability
4Reliability
If separate system-on-chip devices are used for command and monitor lanes, then design diversity is achieved, but manufacturing cost increases
Solution Approach 1:
The patent consolidates multiple separate system-on-chip devices into a single multicore processor device, reducing manufacturing costs associated with assembling and testing multiple discrete components. The integrated design simplifies the supply chain and manufacturing process while maintaining identical safety constraints across all processor cores through a unified fabrication process
Data Source
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AI summary
A control system includes a computing channel and an object control channel. The computing channel includes command and monitor lanes. The command lane has a first processor core with a first core architecture receiving input data and generating first data based on the input data. The monitor lane has a second processor core with second core architecture receiving the input data and generating second data based on the input data. The first core architecture and the second core architecture are dissimilar and implemented in a single system-on chip device. The object control channel corresponds to the computing channel and includes an object control system receiving the command data and generating an object control signal based on the command data to control operation of at least one part of an object system.