Multi-Core RAM EDAC Testing for Avionics Bit-Error Recovery
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Avionics computer systems at high altitudes are vulnerable to single-event upsets caused by cosmic rays, leading to double-bit errors that existing correction methods, such as module resets or newer processor privilege modes, cannot effectively address, especially in multi-core processing environments.
Innovation Solution
A multi-core processor system with a health monitor and RAM error detection and correction (EDAC) module that detects and corrects single-bit errors in system memory, ensuring scalable error correction across all system RAM, including portions mapped to the hypervisor, while maintaining single-point ownership and access, and preventing modifications during testing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If module reset is used to handle bit errors, then error correction is achieved, but system operation continuity is lost
Solution Approach 1:
The patent implements preliminary action by proactively detecting and correcting single-bit errors before they can escalate to double-bit errors that would require a module reset. The health monitor continuously monitors memory integrity and corrects errors in real-time, preventing the need for disruptive reset operations and maintaining system operation continuity.
2Measurement precision
If simultaneous access to RAM is implemented, then error detection capability is improved, but device complexity increases
Solution Approach 1:
The patent introduces an intermediary health monitor component that mediates between the processor partitions and the RAM EDAC test module. This health monitor manages the complexity of simultaneous access coordination, providing a simplified interface for error detection while handling the intricate details of multi-core memory access synchronization and EDAC register management.
3Adaptability or versatility
If memory is mapped to multiple partitions, then system scalability is improved, but access control complexity increases
Solution Approach 1:
The patent applies segmentation by dividing system memory into distinct portions mapped to different processor partitions (first partition, second partitions, hypervisor). Each partition has controlled access to its designated memory portion, simplifying access control while maintaining scalability. The health monitor and RAM EDAC test module operate with single-point ownership to manage these segmented memory regions efficiently.
Data Source
AI summary
A system and method for detection and correction of single-bit errors in a multi-core processing resource (MCPR) of an avionics processing system includes a RAM EDAC testing module called by the MCPR health monitor to access EDAC registers of a system-on-chip module coupled to the MCPR and access memory addresses passed by the MCPR health monitor to detect single-bit errors. Single-bit errors detected in memory mapped to the hypervisor are corrected by the RAM EDAC testing module. Single-bit errors detected in memory associated with a partition or core of the MCPR are corrected by the health monitor running on the particular partition or core with which the memory portion is associated. Single-bit errors may be detected in unmapped memory associated with a partition or core by accessing the unmapped memory via a temporary TLB entry.