Hardware-Enforced Domain Separation in Multicore Shared Cache Systems
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Solution Overview
Problem
Multicore processor systems face security risks due to data co-mingling in shared caches, which existing technologies have not adequately addressed, particularly in configurations with shared caches.
Innovation Solution
A multicore processor system with a separation kernel that enforces static virtual address mappings to isolate memory domains, using memory management units and peripheral access management units to selectively share caches and execute on each core, thereby isolating domains and reducing security risks through hardware-enforced domain separation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If shared caches are used in multicore processor systems, then resource utilization and performance are improved, but data security and domain isolation are compromised due to data co-mingling
Solution Approach 1:
The shared cache is segmented into multiple isolated cache partitions, each assigned to a specific domain. The cache management unit maintains separate cache tags and validity bits for each domain, preventing data co-mingling while allowing multiple domains to share the physical cache resource. This segmentation enables both high resource utilization and strong domain isolation.
Solution Approach 2:
Different regions or partitions of the shared cache are assigned different security attributes and access permissions. Each cache line or set can be associated with a specific domain through domain tags, allowing the cache to provide different levels of access control and isolation for different domains while operating as a unified resource.
2Reliability
If domain isolation is enforced through software-only methods, then data security is improved, but system performance and execution speed deteriorate due to lack of hardware enforcement
Solution Approach 1:
A cache management unit is introduced as an intermediary between the processing cores and the shared cache. This hardware unit automatically enforces domain isolation policies by checking domain tags and cache permissions, eliminating the need for software intervention in every cache access. The hardware enforcement ensures both security and performance by making isolation transparent to the executing code.
Solution Approach 2:
The patent replaces software-based domain isolation mechanisms with hardware-based enforcement in the cache control logic. The cache management unit uses hardware tags, validity bits, and permission bits to automatically enforce domain boundaries, providing both security and performance by eliminating software overhead while maintaining strong isolation guarantees.
3Device complexity
If multiple domains share the same cache without isolation, then device complexity is reduced, but manufacturing precision and security standards cannot be met
Solution Approach 1:
The shared cache structure serves multiple functions simultaneously: it provides high-speed caching for multiple domains, enforces domain isolation through hardware tags, and meets security standards for certified systems. The cache management unit handles multiple domains and security policies within a single unified structure, avoiding the need for completely separate physical caches for each domain.
Data Source
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AI summary
A separation kernel isolating memory domains within a shared system memory (103, 301, 401) is executed on the cores (202) of a multicore processor (101, 201a-201h) having hardware security enforcement for static virtual address mappings, to implement an efficient embedded multi-level security system (100). Shared caches (208, 209) are either disabled or constrained by the same static virtual address mappings using the hardware security enforcement available, to isolate domains accessible to select cores and reduce security risks from data co-mingling.