Multi-Core Architecture Shared Interrupts Power Optimization
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Solution Overview
Problem
Existing microcontrollers with multi-core architecture do not effectively distribute tasks across different cores, leading to inefficiencies in power consumption and performance, as they typically rely on a single resource for managing all tasks, limiting the potential benefits of parallelism and voltage/frequency scaling.
Innovation Solution
A multi-core architecture where tasks triggered by common peripherals can be distributed across multiple cores, with each core having its own memory and peripherals, allowing for independent execution and voltage/frequency scaling to optimize power consumption and performance, using a common memory bus and dedicated interrupt lines for efficient task distribution.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If tasks are managed on a single core in traditional microcontrollers, then device complexity is reduced and ease of operation is improved, but power consumption increases and performance is limited
Solution Approach 1:
The patent divides the task management workload into separate segments by allocating different tasks to different cores. Core 310 handles real-time tasks while core 320 handles non-real-time tasks, allowing each core to operate independently and efficiently, thereby reducing overall power consumption while maintaining manageable complexity through structured task distribution
Solution Approach 2:
The patent changes operational parameters by enabling voltage and frequency scaling on individual cores based on task requirements. Real-time tasks on core 310 can operate at higher frequencies and voltages when needed, while non-real-time tasks on core 320 can use lower power settings, optimizing the balance between complexity management and power consumption
2Use of energy by moving object
If tasks are distributed across multiple cores, then power consumption is reduced through voltage and frequency scaling, but device complexity increases
Solution Approach 1:
The patent implements a universal interrupt handling mechanism that works across multiple cores. The common interrupt line 386 can trigger tasks on either core 310 or core 320 depending on task type, providing multi-functionality that simplifies the interface while enabling complex power optimization strategies through selective task distribution
Solution Approach 2:
The patent uses common memory 340 and common memory bus 380 as intermediaries between cores 310 and 320. This mediator approach allows cores to communicate and share data without direct complex interconnections, reducing the overall system complexity while still enabling effective task distribution and power management
3Ease of operation
If all tasks are executed on one core, then ease of operation is maintained with simple task management, but performance is limited and power consumption increases
Solution Approach 1:
The patent segments tasks into real-time and non-real-time categories, assigning them to different cores based on their performance requirements. This segmentation maintains operational simplicity through clear task classification while significantly improving overall system performance by parallelizing task execution across multiple cores
Solution Approach 2:
The patent employs periodic interrupt-driven task execution where common peripherals trigger tasks at specific intervals. This periodic action structure maintains ease of operation through predictable task scheduling while improving performance by allowing the system to efficiently switch between cores based on periodic interrupt events rather than continuous monitoring
Data Source
AI summary
A multicore architecture is configured to exploit explicit task parallelism to save power by sharing interrupt sources that trigger independent tasks.