Asymmetric Multi-Core Processor Sleep Control During Power Shortage

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Solution Overview

Problem

Security and home automation systems face challenges in maintaining reliable operation during power outages or shortages, as they require continuous power to accurately send and receive critical data, leading to potential undetected alarm conditions.

Innovation Solution

A multi-core processor is used with a master core executing a real-time operating system (RTOS) that periodically transitions between sleep and awake states to manage power consumption, while a slave core executing a full-blown operating system enters a deep sleep state during power shortages, optimizing power usage and ensuring critical tasks are completed.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the processor operates continuously to maintain reliable operation during power outages, then system reliability is improved, but power consumption increases

Engineering Contradiction:
Improvesystem reliabilityVSAvoidpower consumption
Core Design Contradiction:
ReliabilityVSUse of energy by moving object

Solution Approach 1:

The processor is divided into two independent cores: a first core that maintains the real-time operating system and continues operation during power outages, and a second core that enters sleep mode. This segmentation allows critical functions to remain reliable while non-critical functions consume minimal power, resolving the contradiction between system reliability and power consumption.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The system dynamically adjusts the operational state of processor cores based on power availability. During normal operation, both cores are active. During power outages, the second core transitions to sleep mode while the first core remains active. This dynamic adaptation allows the system to maintain reliability when needed while optimizing power consumption when power is limited.

Inventive Principle:
Principle #15Dynamics

2Use of energy by moving object

If the processor enters sleep mode to reduce power consumption during power shortages, then power consumption is reduced, but system response time worsens

Engineering Contradiction:
Improvepower consumptionVSAvoidsystem response time
Core Design Contradiction:
Use of energy by moving objectVSSpeed

Solution Approach 1:

By segmenting the processor into two cores with different functional roles, the system can place the second core in sleep mode to reduce power consumption while the first core remains awake to maintain real-time response capabilities. This segmentation eliminates the need to compromise response time when reducing power consumption.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Different parts of the processing system have different operational characteristics: the first core operates continuously with real-time responsiveness for critical functions, while the second core enters sleep mode for non-critical functions. This local differentiation of operational quality allows power reduction without compromising overall system response time for critical operations.

Inventive Principle:
Principle #3Local quality

3Device complexity

If a single core handles all operations, then device complexity is reduced, but power management capability deteriorates

Engineering Contradiction:
Improveprocessor structureVSAvoidpower management capability
Core Design Contradiction:
Device complexityVSAdaptability or versatility

Solution Approach 1:

The processor is segmented into two cores with distinct responsibilities: the first core handles real-time operating system operations and power management decisions, while the second core handles additional processing tasks. This segmentation provides sophisticated power management capability through coordinated operation modes without introducing excessive complexity, as the segmentation is functionally driven and manageable.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentEP3243111B1Multi-core processor for optimized power consumption in a security and home automation system
Publication Date: 2021.04.21 TYCO SAFETY PRODS CANADA
  • EP3243111B1 patent drawingFigure 1
  • EP3243111B1 patent drawingFigure 2
  • EP3243111B1 patent drawingFigure 3

AI summary

Techniques for using a multi-core processor for optimizing power consumption in a security and home automation system are described. The security and home automation system may include a multi-core processor having a first core and a second core. The first core may be partitioned from the second core to form an asymmetric multi-core processor. The first core is a master core assigned to execute a real time operating system (RTOS) and configured to periodically transition between a partial sleep state and an awake state during a power shortage condition. The second core is a slave core assigned to execute a standard operating system (OS) and configured to enter a deep sleep state during the power shortage condition.