Multi-Core SoC Power Rail Sharing for DVFS Without Area Growth
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Solution Overview
Problem
Current System on Chip (SoC) designs face challenges in optimizing power management for multiple cores, as they often require a single voltage regulator to supply maximum currents to all cores, leading to inefficient power consumption and increased area requirements due to the need for higher current capacities and passive devices.
Innovation Solution
The implementation of a System on Chip (SoC) with multiple cores, each having a dedicated voltage regulator and power gating switches, allowing for per-core dynamic voltage management and frequency scaling, which reduces power consumption by selectively connecting voltage regulators based on core activity and workload.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a single voltage regulator supplies maximum currents to all cores, then all cores can be supported, but power consumption increases and area requirements increase
Solution Approach 1:
The patent divides the power supply system into separate voltage regulators for different core groups (first voltage regulator for first group of cores, second voltage regulator for second group of cores). This segmentation allows each regulator to be sized appropriately for its specific load rather than one regulator being oversized to handle all cores simultaneously, reducing total power consumption and area.
Solution Approach 2:
The patent implements dynamic power management through power gating switches that can selectively connect or disconnect voltage regulators from specific core groups based on operational needs. This dynamic reconfiguration allows the system to optimize power consumption by activating only the necessary voltage regulators when certain cores are active, rather than maintaining maximum capacity continuously.
2Productivity
If a single voltage regulator supplies maximum currents to all cores, then all cores can be supported, but chip area increases due to higher current capacity requirements
Solution Approach 1:
By segmenting the voltage regulation into multiple smaller regulators (first voltage regulator and second voltage regulator), each regulator can be designed with smaller current capacity suitable for its specific core group. This eliminates the need for a single large regulator with maximum current capacity for all cores, thereby reducing the total chip area required for power management components.
Solution Approach 2:
The dynamic power gating mechanism allows the system to flexibly activate only the voltage regulators needed for currently active core groups. This dynamic allocation means the chip area for power management can be optimized rather than reserved for maximum simultaneous core operation, reducing overall chip area while maintaining full core support capability.
3Productivity
If a single voltage regulator supplies maximum currents to all cores, then all cores can be supported, but passive device count increases
Solution Approach 1:
Segmenting the voltage regulation system into multiple regulators reduces the current capacity requirements for each individual regulator. This segmentation directly reduces the number and size of passive devices (such as inductors, capacitors, and resistors) needed in each regulator circuit, as passive device size and count are typically proportional to the current handling capacity required.
Data Source
AI summary
A system on chip (SoC) includes a first core and a second core, first and second power gating switches, and a first power switch. The first power gating switch is arranged between the first core and a first power rail that receives a first voltage, and is selectively turned on in response to a first power gating signal. The second power gating switch is arranged between the second core and a second power rail that receives a second voltage, and is selectively turned on in response to a second power gating signal. The first power switch is arranged between the first power rail and the second power rail, and is selectively turned on in response to a first power control signal to connect the first power gating switch or the second power gating switch both the first power rail and the second power rail.