Multi-Core Split Lock Switching Without Reboot Delays
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Solution Overview
Problem
Existing multi-core processors require lengthy reboot and reinitialization processes to switch between split mode and lock mode, leading to increased processor downtime and decreased performance when handling safety-critical and non-safety-critical applications.
Innovation Solution
A multi-core processor architecture that allows dynamic switching between split and lock modes without rebooting, using a comparator to compare inputs from cores, saving data to memory, and configuring memory and comparator to enable lock mode execution, thereby reducing latency and improving performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the core is configured during boot time to work in lock mode or split mode, then the core can execute safety-critical or non-safety-critical applications with appropriate safety compliance, but switching between modes requires stopping all processing, resetting and rebooting the core which increases processor downtime and decreases overall performance
Solution Approach 1:
The patent implements dynamic mode switching capability that allows the core to transition between split mode and lock mode during runtime without requiring a full reboot. The mode switch controller receives mode switch requests, initiates the switching sequence, and coordinates the transition process, enabling the system to adapt its operational mode dynamically based on application requirements while maintaining continuous processing capability.
Solution Approach 2:
The patent performs preliminary actions by pre-configuring multiple operational modes (split mode and lock mode) within the core architecture during design, and pre-establishing the mode switch controller that can initiate mode transitions. The context information is saved to storage elements before mode switching occurs, and the core is pre-prepared to resume execution in the new mode, reducing the overhead of mode transitions.
2Reliability
If the core is configured during boot time to work in lock mode or split mode, then the core can execute safety-critical or non-safety-critical applications with appropriate safety compliance, but switching between modes requires reinitializing the core over several hundreds of clock cycles which decreases overall performance
Solution Approach 1:
The patent implements dynamic mode switching capability that allows the core to transition between split mode and lock mode during runtime without requiring a full reboot. The mode switch controller receives mode switch requests, initiates the switching sequence, and coordinates the transition process, enabling the system to adapt its operational mode dynamically based on application requirements while maintaining continuous processing capability.
Solution Approach 2:
The patent extracts and separates the mode switching functionality from the full core reinitialization process. The mode switch controller handles mode transitions independently, managing only the necessary changes for mode switching without reinitializing the entire core, thereby significantly reducing the time and resources required for mode transitions.
3Reliability
If separate processing units are dedicated to run only safety-critical applications, then safety compliance is ensured, but the system loses flexibility to trade-off between performance and safety
Solution Approach 1:
The patent implements a universal core design where a single processing core can operate in multiple modes - split mode for non-safety-critical applications and lock mode for safety-critical applications. The mode switch controller enables the core to transition between these modes dynamically, allowing the same hardware resource to serve multiple purposes and满足不同安全级别的应用需求，从而在保持安全合规性的同时提高了系统的灵活性和资源利用率.
Data Source
AI summary
Each core of a multi-core processor is capable of running both safety-critical and non-safety-critical applications. The first core is configured to send a request to the second core to enter into a lock mode to execute the safety-critical application in parallel with the first core. A comparator receives inputs from the first core and the second core and compares the inputs. The second core drives the comparator into a transition state; stops execution of a first application running on the second core; saves data from the second core to memory associated with the second core; and sends an acknowledgment back to the first core in response to the request. The first core, in response to receiving the acknowledgement signal, is further configured to enable the execution of the safety-critical application by both cores in lock mode by configuring the memory and the comparator.