Multi-Core Processing Circuit for Dynamic Stage-Wise Core Allocation
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Solution Overview
Problem
Existing data processing devices face inflexible computing power allocation, leading to insufficient utilization and/or insufficient computing power for specific data processing tasks.
Innovation Solution
A data processing device and method that utilizes a multi-core processor to dynamically allocate computing power based on a preset optimization objective, determining target computing powers for each data processing stage and adjusting core allocation accordingly.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If computing power is allocated in advance to each core for data processing stages, then the device complexity is reduced and ease of operation is improved, but the adaptability and flexibility of computing power allocation deteriorates
Solution Approach 1:
The patent implements dynamic computing power allocation by allowing cores to transition between different data processing stages based on real-time requirements. The allocation is no longer static but adapts dynamically to the actual computing needs of each stage, resolving the contradiction between ease of operation and adaptability.
Solution Approach 2:
The system changes the parameter of computing power allocation from fixed to variable. By adjusting the allocation parameters based on the actual computing requirements of different data processing stages, the system achieves both ease of operation through standardized procedures and adaptability through parameter optimization.
2Ease of manufacture
If computing power is allocated in advance to each core, then the device complexity is reduced, but the productivity and efficiency of data processing deteriorates due to insufficient utilization
Solution Approach 1:
The patent enables dynamic adjustment of computing power allocation to match the actual productivity requirements of each data processing stage. This dynamic approach ensures that computing resources are fully utilized without waste, thereby improving overall productivity while maintaining ease of manufacture through systematic allocation rules.
Solution Approach 2:
The patent makes computing cores universal by allowing them to perform multiple data processing stages rather than being dedicated to a single function. This multi-functionality improves productivity by enabling better resource utilization while maintaining ease of manufacture through standardized core designs that can be flexibly allocated.
3Ease of operation
If computing power is allocated in advance to each core, then the device complexity is reduced and ease of operation is improved, but the computing power sufficiency for specific data processing tasks deteriorates
Solution Approach 1:
The patent implements dynamic computing power allocation that adjusts in real-time to ensure sufficient computing power for each data processing stage. This dynamic approach maintains ease of operation through systematic allocation while improving reliability by ensuring that each stage receives adequate computing resources based on actual needs.
4Device complexity
If fixed core allocation is used for data processing stages, then the device complexity is reduced, but the loss of time due to inefficient resource utilization increases
Solution Approach 1:
The patent reduces device complexity by implementing a systematic dynamic allocation mechanism while simultaneously reducing time loss. The dynamic nature of the allocation allows computing cores to be efficiently utilized across different data processing stages, eliminating idle time and improving overall processing speed without significantly increasing system complexity.
Data Source
AI summary
A processing circuit includes a multi-core processor including a K-core sub-processor(s) for participating in a target process in which the target data is subjected to N data processing stages to generate result data. The processing circuit obtains the target data and determines N target computing powers corresponding to the N data processing stages; and in the target process, determines the allocation of the K cores in executing the N data processing stages based on the N target computing powers and a preset optimization objective. It can be seen that through the solution provided by the present disclosure, during the operation of the data processing device, the computing power provided by the K cores for the N data processing stages can be determined, and the target computing power corresponding to each data processing stage can be adaptively allocated, which is beneficial to improving the flexibility of computing power allocation.