Multi-Core Strobe Calibration for PVT-Tolerant Semiconductor Timing
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In semiconductor devices with multiple core chips, strobe signals generated at different times due to process, voltage, and temperature variations, leading to misalignment and inefficiencies in data access.
Innovation Solution
A semiconductor device with a base chip that outputs strobe and control signals and adjusts delay amounts through calibration signals to align strobe signals across multiple core chips using training operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple core chips are used in a semiconductor device, then the integration and performance are improved, but the strobe signals generated at different times due to PVT variations cause misalignment and reduce data access efficiency
Solution Approach 1:
The patent implements preliminary action by performing strobe signal calibration before normal data access operations. The calibration process adjusts delay amounts in advance to compensate for PVT variations, ensuring that strobe signals from multiple core chips are properly aligned during subsequent data access operations, thereby resolving the misalignment issue while maintaining high data access efficiency
Solution Approach 2:
The patent employs feedback mechanisms through calibration operations that monitor and adjust strobe signal timing. The system uses feedback from timing measurements to dynamically adjust delay amounts in each core chip's strobe signal generation circuit, creating a closed-loop control system that maintains signal alignment despite PVT variations, thus improving both reliability and productivity
2Reliability
If calibration operations are implemented to align strobe signals, then signal synchronization is improved, but the device complexity increases due to additional control signals and training operations
Solution Approach 1:
The patent applies universality by designing a multi-functional calibration control circuit that performs multiple tasks: generating calibration control signals, measuring timing differences, calculating delay amounts, and coordinating training operations across multiple core chips. This single circuit structure handles various calibration functions, reducing the need for separate dedicated circuits for each function and thereby limiting the increase in device complexity while achieving reliable signal synchronization
Solution Approach 2:
The patent uses periodic action through structured calibration sequences that operate in distinct phases (training operations). The calibration process is divided into periodic training phases where different core chips are calibrated sequentially, with control signals enabling specific calibration operations at designated times. This periodic approach organizes the calibration complexity into manageable time-sliced operations, improving synchronization while keeping the control structure systematic and predictable
Data Source
AI summary
A semiconductor device includes a base chip configured to output a strobe signal and a control signal and to output a first update signal and a second update signal in response to receiving first and second core strobe signals, a first core chip configured to generate the first core strobe signal by delaying the strobe signal by a first delay amount while a pulse of the control signal is input, to output the first core strobe signal to the base chip, and to calibrate the first delay amount while the first update signal is enabled, and a second core chip configured to generate the second core strobe signal by delaying the strobe signal by a second delay amount when a pulse of the control signal is input, to output the second core strobe signal to the base chip, and to calibrate the second delay amount while the second update signal is enabled.