Multi-Core Swap Memory Page Table Management
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The inefficiency of using a non-volatile memory device as a swap memory due to its faster access speed and complex functions like wear leveling or garbage collection, which complicates data swapping operations.
Innovation Solution
A data swapping method utilizing a multi-core processor to search for an empty page in a swap memory, select a page from the main memory, and swap data to the empty page, while updating page tables and determining waiting times based on continuity of swap memory addresses or expected busy times to optimize data transfer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a non-volatile memory device is used as a swap memory, then access speed is improved compared to HDD, but operation efficiency deteriorates due to wear leveling and garbage collection functions
Solution Approach 1:
The patent divides the swap memory into multiple pages and uses multiple cores to handle different page swapping operations simultaneously. This segmentation allows parallel processing of swap operations, improving overall efficiency while managing the complexity introduced by wear leveling and garbage collection functions.
Solution Approach 2:
The patent implements a page table that pre-stores information about pages to be swapped, including their locations and status. This preliminary organization of swap information allows the system to quickly identify and execute swap operations without being hindered by the overhead of wear leveling and garbage collection during active swapping.
2Productivity
If multiple cores are used for swap operations, then data transfer speed is improved, but system complexity increases
Solution Approach 1:
The patent designs the page table structure to serve multiple purposes: tracking swap pages, storing location information, and managing multiple cores' operations. This universal structure allows the same mechanism to handle complexity from multiple cores without requiring separate management systems for each core.
Solution Approach 2:
The patent introduces the page table as an intermediary data structure that mediates between multiple cores and the swap memory. This intermediary centralizes the management of swap operations, allowing multiple cores to work in parallel while maintaining system coherence and reducing direct complexity in core-to-memory interactions.
3Productivity
If swap operations are performed frequently, then memory management efficiency is improved, but wear on non-volatile memory increases
Solution Approach 1:
The patent pre-organizes swap information in the page table, identifying pages that need to be swapped before actual swap operations begin. This preliminary identification allows the system to batch and optimize swap operations, reducing the total number of write operations to non-volatile memory while maintaining effective memory management.
Solution Approach 2:
The patent implements wear leveling and garbage collection as automatic background functions managed by the non-volatile memory device itself. This self-service approach allows frequent swap operations to occur without manual intervention, while the memory device autonomously manages its own wear distribution and data integrity, maintaining reliability despite high usage.
Data Source
AI summary
A swapping method performed using a data processing device, which includes a processor including a plurality of cores, the swapping method including searching for an empty page of a swap memory in response to the swap memory being connected to the data processing device, the search being performed by using at least one core of the plurality of cores, selecting a page to be swapped from a main memory of the data processing device, the selection being performed by using the at least one core by accessing a corresponding main memory list among a plurality of main memory lists, and swapping data of the page selected to be swapped to the empty page, the swapping being performed by using the at least one core.