Multicore Processor Synchronization via Shared Memory Mediator
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Solution Overview
Problem
In multicore systems, synchronizing processor cores for decoding video and audio data under different operating systems is challenging, leading to potential timing deviations between sound and video output, which can degrade the quality of moving image reproduction.
Innovation Solution
A data processing system with multiple data process control units and a shared memory region that synchronizes start timings and adjusts output timings based on reference clocks and lapse time deviations, allowing each unit to determine execution status independently without a predetermined master-servant relationship.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If processor cores execute processes individually to achieve parallelization, then productivity is improved, but synchronization between cores becomes difficult to maintain
Solution Approach 1:
The patent introduces a shared memory region as an intermediary mechanism that enables synchronization between independently executing processor cores. Each core can read/write synchronization values to this shared region, allowing them to coordinate their operations without direct communication or a master-servant hierarchy. This resolves the contradiction by maintaining individual core autonomy while providing a reliable synchronization channel through the shared memory mediator.
2Reliability
If a master-servant relationship is established for synchronization, then synchronization reliability is improved, but device complexity increases
Solution Approach 1:
The patent segments the synchronization function into independent operations that each processor core can perform autonomously. Instead of a centralized master controller, each core independently manages its own synchronization state by writing to and reading from the shared memory region. This segmentation eliminates the need for complex master-servant relationship management while maintaining reliable synchronization through distributed, simple operations.
3Adaptability or versatility
If different operating systems control audio and video decoding on different processor cores, then adaptability is improved, but timing synchronization between audio and video output deteriorates
Solution Approach 1:
The patent implements a feedback mechanism where each processor core continuously monitors the lapse time since the last synchronized operation and compares it against a reference value stored in the shared memory region. When timing deviation exceeds a threshold, the system adjusts the output timing of the affected core to realign with the reference. This feedback loop enables different operating systems running on separate cores to maintain precise timing synchronization between audio and video output while preserving their independence and adaptability.
Data Source
AI summary
The present invention easily realizes synchronization between processor cores in a multicore system. A data processing system receiving a group of data of different kinds from the outside and performing data processes by kinds includes: a plurality of data process control units corresponding to the kinds of the data group and performing data processes on the data group of corresponding kinds; and a memory unit which can be accessed by the data process control units and has a first region storing a value indicating whether the data process by the data process control units can be executed or not. Each of the data process control units updates the value in the first region on completion of preparation for executing the data process of itself and, when the value in the first region becomes a predetermined value, synchronizes start timings of the data processes and executes the data processes.