Multi-Core Synchronization Using Counting Semaphores and Message Queues
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Solution Overview
Problem
Existing multi-core systems face inefficiencies in system scheduling and resource consumption due to the need for interrupts during synchronization and communication between multiple cores, particularly when multiple processors compete for shared resources.
Innovation Solution
A method and apparatus for synchronous processing in a multi-core system that uses a counting semaphore and control messages to manage task processing across groups of processing devices, eliminating the need for interrupts by initializing and notifying devices through internal caches and message interfaces.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If interrupts are used for synchronization and communication between multiple cores, then processing can be coordinated between cores, but system scheduling efficiency decreases and resource consumption increases
Solution Approach 1:
The patent extracts the interrupt handling mechanism from the synchronization and communication process between multiple cores. Instead of using interrupts to notify cores of events, the invention implements a message queue mechanism where messages are directly placed in memory locations accessible to target cores, eliminating the need for interrupt controllers and interrupt handling overhead while maintaining reliable coordination.
Solution Approach 2:
The patent introduces message queues as intermediary structures between sending and receiving cores. These queues act as buffers that store messages in memory, allowing cores to communicate asynchronously without requiring synchronous interrupt handling. The message queue mechanism mediates the communication process, enabling efficient scheduling while maintaining coordination reliability.
2Reliability
If interrupts are used for synchronization and communication between multiple cores, then processing can be coordinated between cores, but resource consumption increases
Solution Approach 1:
The patent removes the interrupt handling infrastructure from the system, including interrupt controllers, interrupt vectors, and associated processing overhead. By extracting this mechanism and replacing it with direct memory-based message queues, the system reduces resource consumption while maintaining the ability to coordinate between cores through asynchronous message passing.
3Reliability
If multiple processors compete for a mutually exclusive cache through interrupts, then resource access can be controlled, but system scheduling efficiency decreases
Solution Approach 1:
The patent introduces a semaphore processing unit with an internal message queue as an intermediary for resource access control. Instead of using interrupts to manage mutually exclusive cache access, the invention implements a counting semaphore mechanism where processors send requests through a message queue. The semaphore unit manages cache allocation and releases interrupts only when resources are available, improving scheduling efficiency while maintaining reliable access control.
4Reliability
If a semaphore processing unit uses interrupts to manage mutually exclusive cache access, then resource allocation can be controlled, but system scheduling efficiency decreases
Solution Approach 1:
The patent extracts the interrupt handling step from the semaphore processing workflow. The semaphore processing unit is redesigned to use an internal message queue for managing resource requests and allocations. By eliminating interrupt-based notification and using direct memory-based message passing, the system reduces scheduling overhead and time loss while maintaining controlled resource allocation through the counting semaphore mechanism.
Data Source
AI summary
Embodiments of the present invention relate to the field of communications network technologies and provide a method and an apparatus for synchronization processing based on a multi-core system, which can improve efficiency in system scheduling and consume fewer resources. According to the solutions provided in the present invention, an initialization setting is sent by any processing device in a first group of processing devices that synchronously process a same current task and initialization is performed; then a notification message sent by any processing device in the first group of processing devices is received and 1 is subtracted from a value of a counting semaphore; and when the value of the counting semaphore is 0, a control message is sent to a second group of processing devices through a message sending interface. The solutions provided in the present invention are applicable to processing synchronization and communication between multiple modules.