Multi-Core Task Allocation via State Register Monitoring

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Solution Overview

Problem

Existing multi-core processor designs face inefficiencies in task processing due to unbalanced task demands, leading to idle processor cores that consume power even when not needed, and waking up entire processors to process tasks affects efficiency.

Innovation Solution

A system and method for task allocation in multi-core processors that utilize state registers to monitor core states and allocate tasks based on priority, allowing direct task transmission to idle cores and buffering for busy cores, enabling flexible configuration according to application scenarios and data traffic.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Use of energy by stationary object

If the whole processor enters Sleep state to reduce power consumption, then power consumption is reduced, but real-time data cannot be processed and task processing efficiency is affected

Engineering Contradiction:
Improvepower consumptionVSAvoidtask processing efficiency
Core Design Contradiction:
Use of energy by stationary objectVSProductivity

Solution Approach 1:

The processor is divided into multiple independent cores, each capable of operating in different states (Idle, Wait, Sleep, Off). This segmentation allows the system to reduce power consumption by putting individual cores to sleep while maintaining others in active states for real-time processing.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The system dynamically adjusts the operational state of each processor core based on real-time task allocation needs and power consumption requirements. The state register continuously monitors and updates the state of each core, enabling flexible transitions between power-saving and performance modes.

Inventive Principle:
Principle #15Dynamics

2Productivity

If tasks are allocated to idle processor cores, then task processing efficiency is improved, but power consumption increases due to unbalanced task demands

Engineering Contradiction:
Improvetask processing efficiencyVSAvoidpower consumption
Core Design Contradiction:
ProductivityVSUse of energy by stationary object

Solution Approach 1:

The state register provides continuous feedback on the operational state of each processor core to the task allocator. This feedback mechanism enables the system to make informed decisions about task allocation, matching tasks to appropriate core states and optimizing the balance between processing efficiency and power consumption.

Inventive Principle:
Principle #23Feedback

Solution Approach 2:

The system changes the operational parameters (state) of processor cores based on task requirements. By dynamically adjusting which cores are active, in wait state, or in sleep state, the system optimizes power consumption while maintaining task processing efficiency.

Inventive Principle:
Principle #35Parameter changes

3Power

If the processor wakes up to process tasks, then task processing capability is restored, but task processing efficiency is affected due to wake-up time

Engineering Contradiction:
Improveprocessing capabilityVSAvoidwake-up time
Core Design Contradiction:
PowerVSLoss of time

Solution Approach 1:

The system maintains processor cores in a Wait state with preserved site information, allowing for rapid wake-up and task processing. This preliminary preparation reduces the wake-up time compared to waking from a full Sleep state, while still providing power savings during idle periods.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS8763002B2Method, system, and apparatus for task allocation of multi-core processor
Publication Date: 2014.06.24 HUAWEI TECH CO LTD
  • US8763002B2 patent drawing
  • US8763002B2 patent drawing
  • US8763002B2 patent drawing

AI summary

A system for task allocation of a multi-core processor is provided. The system includes a task allocator and a plurality of sub-processing systems. Each of the sub-processing systems comprises a state register, a processor core, and a buffer, the state register is configured to recognize state of the sub-processing systems, and transmit state information of the sub-processing systems to the task allocator, the state information comprises: a first state bit configured to indicate whether sub-processing systems are in Idle state; and a second state bit configured to indicate a specific state of the sub-processing systems. The task allocator is configured to allocate task to the sub-processing systems according to a priority determined by the state information sent by the state registers of the sub-processing systems.