Multicore Task Scheduling via CPU-Bound Priority and Core Binding

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Solution Overview

Problem

Existing multicore processor scheduling mechanisms face inefficiencies when handling CPU-bound and non-CPU bound tasks with equal priority, leading to core idling, missed deadlines, and reduced system utilization due to priority inversion and FIFO-based scheduling.

Innovation Solution

A method that prioritizes CPU-bound tasks over non-CPU bound tasks and binds non-CPU bound tasks to specific cores during priority inversion, optimizing task scheduling by considering task types and past execution statistics to improve load balancing and power consumption.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of operation

If FIFO scheduling mechanism is used for tasks with equal priority, then scheduling simplicity is maintained, but core idling occurs and system utilization decreases

Engineering Contradiction:
Improvescheduling simplicityVSAvoidsystem utilization
Core Design Contradiction:
Ease of operationVSProductivity

Solution Approach 1:

The patent applies local quality by differentiating scheduling treatment based on task type. Instead of uniform FIFO scheduling for all equal-priority tasks, the system identifies CPU-bound tasks and gives them scheduling preference over non-CPU-bound tasks, creating localized optimization in the scheduling queue structure

Inventive Principle:
Principle #3Local quality

2Reliability

If non-CPU bound tasks are migrated to another CPU based on priority inversion, then priority inversion is handled, but cache misses increase and system efficiency reduces

Engineering Contradiction:
Improvepriority inversion handlingVSAvoidsystem efficiency
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent applies preliminary action by proactively binding non-CPU-bound tasks to specific cores before priority inversion occurs. When a non-CPU-bound task is identified, it is pre-bound to a core, preventing subsequent migration and the associated cache misses when priority inversion happens

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent introduces core binding as an intermediary mechanism between the task and the CPU. This binding acts as a mediator that prevents direct migration of non-CPU-bound tasks, thereby avoiding cache invalidation and maintaining system efficiency while still handling priority inversion

Inventive Principle:
Principle #24Intermediary (Mediator)

3Ease of operation

If CPU-bound tasks are not prioritized over non-CPU bound tasks, then FIFO order is maintained, but deadlines are missed and response time increases

Engineering Contradiction:
Improvescheduling orderVSAvoiddeadline miss
Core Design Contradiction:
Ease of operationVSLoss of time

Solution Approach 1:

The patent applies parameter changes by modifying the scheduling priority parameter dynamically based on task type. CPU-bound tasks are assigned a higher effective priority parameter than non-CPU-bound tasks even when their base priority levels are equal, changing the execution order parameter to favor CPU-bound tasks

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS11055129B2Method, system, apparatus, and/or non-transitory computer readable medium for the scheduling of a plurality of operating system tasks on a multicore processor and/or multi-processor system
Publication Date: 2021.07.06 SAMSUNG ELECTRONICS CO LTD
  • US11055129B2 patent drawing
  • US11055129B2 patent drawing
  • US11055129B2 patent drawing

AI summary

Various example embodiments herein provide a computerized method for scheduling a plurality of tasks for an operating system on a multicore processor. The method includes identifying the plurality of tasks to be executed on the multicore processor and determining a task schedule for scheduling of the plurality of tasks by providing a higher preference to the CPU-bound task than the non CPU-bound task. Further, the method includes scheduling the plurality of tasks on the multicore processor based on the task schedule.