Multicore Thread Debugging via Hardware Extraction
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Solution Overview
Problem
Debugging in multicore architectures is challenging due to the Heisenberg bug (probe effect), where debug code alters thread timing, masking bugs and affecting performance measurements, and existing solutions lack portability and reusability.
Innovation Solution
A method and apparatus for monitoring thread execution within a multicore processor architecture that compares thread parameter indicators with predefined criteria, enabling thread-level debugging without additional code, using a thread-level software debug controller with monitor logic for thread allocation and execution monitoring.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Difficulty of detecting and measuring
If debug code is added to monitor thread execution, then debugging capability is improved, but thread timing is altered causing the probe effect that masks bugs
Solution Approach 1:
The patent extracts the monitoring function from software debug code and implements it in hardware within the processor element. The monitoring logic is separated into dedicated hardware circuits that observe thread execution without inserting executable instructions, thereby eliminating the probe effect while maintaining debugging capability.
Solution Approach 2:
The patent introduces hardware monitoring logic as an intermediary between the thread execution units and the debug interface. This intermediary captures thread execution information through hardware signals and state observations rather than through software instrumentation, preventing timing alterations while enabling comprehensive debugging.
2Difficulty of detecting and measuring
If extensive debug code is present in the build, then system diagnostics are enhanced, but performance measurements are affected due to cache and bus performance degradation
Solution Approach 1:
The patent extracts diagnostic functionality from software debug code and implements it in hardware. The monitoring logic observes cache and bus operations through hardware signals, eliminating the need for extensive debug code that would otherwise degrade performance measurements while second-order effects.
3Reliability
If thread level monitoring is implemented without additional code, then probe effect is reduced, but monitoring capability must be built into the processor architecture
Solution Approach 1:
The patent merges the monitoring logic with the existing processor element structure. The monitoring circuits are integrated into the processor element's existing control and data paths, sharing hardware resources with the execution units rather than adding completely separate monitoring subsystems.
Solution Approach 2:
The patent designs the monitoring logic to serve multiple functions: thread execution monitoring, performance measurement, and debugging. The same hardware circuits that track thread state for timing accuracy also capture performance data, reducing the need for separate specialized hardware while maintaining reliability.
Data Source
AI summary
According to a first aspect of the present invention, there is provided a method of monitoring thread execution within a multicore processor architecture which comprises a plurality of interconnected processor elements for processing the threads, the method comprising receiving a plurality of thread parameter indicators indicative of one or more parameters relating to the function and/or identity of a thread or threads comparing at least some of the thread parameter indicators with a first plurality of predefined criteria each representative of an indicator of interest and generating an output consequential upon thread parameter indicators which have been identified to be of interest as a result of the said comparison.