Multicore Processor Thread Scheduling for Security and Load Balancing

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Solution Overview

Problem

In multicore processors, not all processing power is utilized efficiently, and there is a need to meet security requirements for threads, which can be challenging due to varying instruction sets and secure states among processor cores.

Innovation Solution

A scheduling algorithm that dynamically selects processor cores based on security requirements, changes secure states, and performs load balancing to ensure efficient execution of threads across cores with different instruction sets and secure modes.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If threads are scheduled on processor cores with different instruction sets and secure states, then security requirements can be met and processing power utilization is improved, but the complexity of scheduling and core selection increases

Engineering Contradiction:
Improveprocessing power utilizationVSAvoidscheduling complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent applies parameter changes by dynamically selecting processor cores based on varying parameters such as security requirements, instruction set compatibility, and current core states. The scheduling algorithm changes the selection criteria according to the specific needs of each thread, matching threads to cores that satisfy their security and instruction set requirements while optimizing overall processor utilization.

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The scheduling algorithm implements dynamics by continuously adapting core selection based on real-time system state. When a thread needs to be scheduled, the algorithm dynamically evaluates which cores are available, their current security states, and their instruction set compatibility, then makes scheduling decisions that optimize both security requirements and processing power utilization without requiring static assignment.

Inventive Principle:
Principle #15Dynamics

2Reliability

If processor cores are dynamically switched to different secure states to meet thread requirements, then security requirements are fulfilled, but the time required for state changes and thread scheduling increases

Engineering Contradiction:
Improvesecurity requirement fulfillmentVSAvoidscheduling time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent applies preliminary action by pre-establishing the relationship between thread security requirements and compatible processor cores. The scheduling algorithm maintains knowledge of which cores can satisfy which security requirements and instruction set needs, allowing it to make rapid scheduling decisions without requiring time-consuming state changes or complex runtime evaluations of core capabilities.

Inventive Principle:
Principle #10Preliminary action

3Productivity

If load balancing is performed across processor cores with different capabilities, then processing efficiency is improved, but the complexity of evaluating and selecting optimal cores increases

Engineering Contradiction:
Improveprocessing efficiencyVSAvoidcore evaluation complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent applies local quality by evaluating processor cores based on their specific local characteristics such as instruction set support, security state capabilities, and current workload. Rather than treating all cores uniformly, the scheduling algorithm assesses each core's unique properties and matches threads to cores whose local qualities best satisfy the thread's requirements, thereby improving processing efficiency while managing evaluation complexity through focused, attribute-specific assessment.

Inventive Principle:
Principle #3Local quality

Data Source

PatentEP2850555B1Method in a processor, an apparatus and a computer program product
Publication Date: 2022.11.30 NOKIA TECHNOLOGIES OY
  • EP2850555B1 patent drawingFigure 1
  • EP2850555B1 patent drawingFigure 2~4
  • EP2850555B1 patent drawingFigure 3

AI summary

There is disclosed a method in which information relating to a sequence of instructions of a thread is examined to determine a security condition of the thread. It is further determined by using the security condition which processor core of a multicore processor has an appropriate security mode to fulfil the security condition. If the determining indicates that one or more processor cores of the multicore processor has the appropriate security mode are available, one of the one or more processor cores is selected as a potential processor core to execute the sequence of instructions of the thread. There is also disclosed an apparatus and a computer program product to implement the method.