Multicore Processor UFS Control Using Extended Doorbell Registers
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Solution Overview
Problem
Existing UFS interfaces in multi-core processors face challenges in efficiently coordinating the collaboration of multiple processor cores for data transmission and storage operations, leading to suboptimal access efficiency and interrupt response times.
Innovation Solution
The implementation of extended doorbell registers and feedback registers for each processor core in the UFS interface, allowing independent and non-interfering access and control over instruction delivery and interrupt feedback, along with flexible control mechanisms to enhance efficiency and compatibility with UFS protocols.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If multiple processor cores share a single doorbell register for UFS interface access, then device complexity is reduced, but processor cores interfere with each other causing decreased UFS access efficiency
Solution Approach 1:
The patent segments the shared doorbell register into multiple independent extended doorbell registers, with each processor core having its own dedicated register. This segmentation eliminates interference between cores while maintaining a relatively simple overall interface structure, resolving the contradiction between device complexity and access efficiency.
2Reliability
If processor cores use lock mechanisms to coordinate access to shared registers, then data consistency is improved, but access time increases due to locking and unlocking operations
Solution Approach 1:
By segmenting the shared register into dedicated extended doorbell registers for each processor core, the patent eliminates the need for lock mechanisms entirely. Each core can access its own register independently without waiting for locks or worrying about data consistency with other cores, thus eliminating both the reliability concerns and time losses associated with locking.
3Stability of the object's composition
If processor cores wait for each other to complete register access, then access coordination is improved, but overall processing speed decreases
Solution Approach 1:
The patent assigns dedicated extended doorbell registers to each processor core, allowing simultaneous independent access without waiting or coordination. This segmentation maintains stable access patterns while dramatically increasing processing speed by eliminating wait states and inter-core dependencies.
4Device complexity
If multiple processor cores share interrupt feedback mechanisms, then device complexity is reduced, but interrupt response time increases due to coordination overhead
Solution Approach 1:
The patent segments the shared feedback mechanism into dedicated feedback paths for each processor core through corresponding extended doorbell registers. This allows interrupts to be delivered directly to the appropriate core without coordination overhead, improving response time while maintaining manageable complexity through the systematic segmentation approach.
Data Source
AI summary
The present disclosure relates to processors, universal flash storage (UFS) control methods, and computer systems. One example processor includes a first processor core, a second processor core, a host controller register (HCI), and a service delivery subsystem (SDS). The HCI includes a first extended doorbell register and a second extended doorbell register. The first processor core may invoke, by using the first extended doorbell register, the HCI to provide first instruction information for the SDS, and the second processor core may invoke, by using the second extended doorbell register, the HCI to provide second instruction information for the SDS.