Multi-Core Processor Reconfiguration for Unified Core Execution
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Solution Overview
Problem
Conventional simultaneous multithreading (SMT) techniques in CPU cores lead to inefficiencies, design complexities, and security vulnerabilities due to resource sharing and dynamic assignment, resulting in performance degradation, deadlocks, livelocks, and susceptibility to side-channel attacks.
Innovation Solution
A processor that can dynamically reconfigure between multi-core and unified core configurations, enabling static partitioning of resources and pipelines to allow independent execution of threads, reducing resource sharing and minimizing interaction, thereby avoiding performance variability and security issues.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If simultaneous multithreading (SMT) techniques are used to execute multiple threads on a single core, then thread utilization is improved, but resource sharing and dynamic assignment cause performance degradation, deadlocks, livelocks, and security vulnerabilities
Solution Approach 1:
The processor is divided into multiple independent cores, each with its own dedicated resources (pipeline, execution units, caches). This segmentation eliminates resource sharing between threads, preventing deadlocks, livelocks, and side-channel attacks while maintaining high thread utilization through parallel execution on multiple cores.
2Productivity
If high-performance CPU cores are designed to improve performance, then processing capability is enhanced, but the chip area occupied by CPU cores increases
Solution Approach 1:
Multiple cores can be dynamically merged into a unified core configuration when only one thread needs high-performance execution. This merging consolidates resources into a single powerful core, reducing the active chip area while maintaining high processing performance for the active thread.
3Productivity
If multiple cores operate in parallel to execute multiple threads, then throughput is improved, but resource contention and interaction increase causing performance variability
Solution Approach 1:
Each core is fully segmented with dedicated resources, eliminating resource contention between threads. This segmentation ensures predictable performance by removing interactions and contentions, while multiple cores still operate in parallel to maintain high throughput.
4Productivity
If resources are dynamically assigned between threads in SMT, then resource utilization is improved, but design complexity and susceptibility to side-channel attacks increase
Solution Approach 1:
Resources are statically allocated to each core rather than dynamically shared, simplifying the design by eliminating complex resource management logic. This static allocation also prevents side-channel attacks by ensuring complete isolation between threads on different cores.
Solution Approach 2:
The processor can dynamically switch between multi-core mode and unified core mode, providing multi-functionality. In unified core mode, all resources are dedicated to a single thread for maximum performance, while in multi-core mode, resources are distributed across multiple cores for parallel thread execution.
Data Source
AI summary
A first thread is executed in a first pipeline of a first core of an integrated circuit (IC). The first core includes a first set of hardware structures. A second thread is executed in a second pipeline of a second core of the IC. The second core includes a second set of hardware structures. In response to a command to operate the IC with a unified core, the first core is combined with the second core to obtain the unified core. To unify the first core, the first pipeline is unified with the second pipeline to obtain a unified pipeline, and the first set of hardware structures is unified with the second set of hardware structures to obtain a unified set of hardware structures. A single thread is executed in the unified pipeline of the unified core using the unified set of hardware structures.