Multi-Core VLSI Timing Skew Synchronization via Self-Test
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Solution Overview
Problem
Synchronizing the timing of multiple cores in multi-core integrated circuits is challenging due to subtle manufacturing variations, leading to distinct critical path timings and timing skew between cores.
Innovation Solution
A method that uses self-test circuitry, such as logic built-in self-test (LBIST), to generate response signatures for each core, compare them, and adjust local clock buffers to match the reference core's signature, thereby synchronizing the cores.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple cores operate independently with asynchronous processing, then processing efficiency is improved, but timing synchronization between cores deteriorates
Solution Approach 1:
The patent adjusts the clock buffer parameters of individual cores to compensate for manufacturing variations. By changing the clock buffer delay parameters, each core's timing is tuned to match the reference core, enabling synchronous operation while maintaining independent processing capabilities
Solution Approach 2:
The system uses built-in self-test circuitry and response signature comparison to automatically detect timing skew between cores. The multi-core system self-diagnoses its own timing synchronization status and triggers adjustments without external intervention, maintaining both independence and synchronization
2Manufacturing precision
If local clock buffers are adjusted to match timing, then timing skew is reduced, but device complexity increases
Solution Approach 1:
The response signature generation circuitry serves dual purposes: it tests core functionality during manufacturing and measures timing characteristics for synchronization. This multi-functional approach avoids adding dedicated timing measurement circuits, reducing overall complexity while achieving precise timing adjustment
Solution Approach 2:
The patent introduces response signatures as an intermediary mechanism to indirectly measure timing skew. Instead of directly measuring clock signals or adding complex timing analysis circuits, the system uses the response signature comparison as a mediator to detect timing differences and guide clock buffer adjustments
3Measurement precision
If response signature comparison is used to detect timing skew, then measurement precision is improved, but device complexity increases
Solution Approach 1:
The patent combines the self-test functionality with the timing measurement function into a single integrated system. The response signature generation and comparison circuits serve both defect detection and timing skew measurement purposes, eliminating the need for separate timing analysis infrastructure and reducing overall system complexity
Data Source
AI summary
A method for adjusting timing of multiple cores within an integrated circuit includes selecting a reference core and a target core from among a plurality of cores of an integrated circuit. Self-test circuitry of the integrated circuit is used to generate a response signature for each of the reference core and the target core. The response signature of the reference core is compared with the response signature of the target core. A local clock buffer of the target core is adjusted until the response signature of the target core matches the response signature of the reference core.