Multicore Processor Independent Voltage Frequency Control

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Solution Overview

Problem

The increasing complexity and power requirements of integrated circuits, particularly in computing systems, lead to significant energy consumption and thermal management issues, necessitating efficient power and performance optimization techniques to reduce energy usage and enhance performance.

Innovation Solution

The implementation of a multicore processor with fully integrated voltage regulation (FIVR) allows individual cores to operate at independent voltage and frequency points, enabling dynamic power/performance management through features like Per Core P-States (PCPS), uncore frequency scaling (UFS), and energy-efficient turbo (EET), which are configurable to optimize power consumption and performance based on workload and thermal constraints.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Loss of energy

If multiple cores operate at independent performance states, then power consumption is optimized, but system complexity increases

Engineering Contradiction:
Improvepower consumptionVSAvoidsystem complexity
Core Design Contradiction:
Loss of energyVSDevice complexity

Solution Approach 1:

The patent divides the processor into multiple independent cores, each capable of operating at different performance states. Each core can be independently controlled to operate at appropriate performance levels based on workload requirements, enabling fine-grained power management while maintaining system functionality.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent implements dynamic performance state adjustment for each core based on real-time workload conditions. The system can dynamically transition cores between different performance states (P-states) and power states (C-states), allowing adaptive power optimization without requiring static configuration.

Inventive Principle:
Principle #15Dynamics

2Productivity

If cores operate at higher frequency, then performance is improved, but energy consumption increases

Engineering Contradiction:
ImproveperformanceVSAvoidenergy consumption
Core Design Contradiction:
ProductivityVSUse of energy by moving object

Solution Approach 1:

The patent utilizes multiple performance states (P0-PN) that correspond to different frequency and voltage combinations. The system can select appropriate P-states based on workload requirements, dynamically changing operating parameters to match performance needs while minimizing energy consumption.

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The patent implements periodic monitoring and adjustment of core performance states based on workload conditions. The system continuously evaluates whether cores should transition between performance states and power states, making periodic optimizations to balance performance and energy consumption.

Inventive Principle:
Principle #19Periodic action

3Loss of energy

If voltage regulation is fully integrated per core, then power optimization is enhanced, but device complexity increases

Engineering Contradiction:
Improvepower optimizationVSAvoiddevice complexity
Core Design Contradiction:
Loss of energyVSDevice complexity

Solution Approach 1:

The patent integrates voltage regulation functionality directly into each core, combining power management functions with core operations. This integration eliminates the need for separate external voltage regulation circuits for each core, reducing overall system complexity while maintaining fine-grained power control capabilities.

Inventive Principle:
Principle #5Merging (Combining)

Data Source

PatentUS11237614B2Multicore processor with a control register storing an indicator that two or more cores are to operate at independent performance states
Publication Date: 2022.02.01 INTEL CORP
  • US11237614B2 patent drawing
  • US11237614B2 patent drawing
  • US11237614B2 patent drawing

AI summary

In one embodiment, a multicore processor includes cores that can independently execute instructions, each at an independent voltage and frequency. The processor may include a power controller having logic to provide for configurability of power management features of the processor. One such feature enables at least one core to operate at an independent performance state based on a state of a single power domain indicator present in a control register. Other embodiments are described and claimed.