Multi-Core Chip Voltage-Frequency Optimization
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Solution Overview
Problem
Multi-core processor chips face performance loss due to regional technology variability, which is addressed by maintaining synchronous operation through system clock frequency changes and local core Vdd settings, resulting in suboptimal performance across cores.
Innovation Solution
Determining individual Vdd-frequency characteristics for each core, saving this data, and configuring cores for optimum power consumption and performance based on workload, using error detection circuitry and voltage control to adjust frequencies and voltages dynamically.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If synchronous operation is maintained by changing system clock frequency and modifying local core Vdd settings to deal with regional technology variability, then operational reliability is improved, but system performance deteriorates due to operating at the lowest-common frequency
Solution Approach 1:
The patent segments the multi-core chip into individually controllable core domains, each with its own voltage and frequency control. This allows each core to operate at its optimal frequency determined by its specific Vdd-frequency characteristics, rather than forcing all cores to run at a common frequency. The segmentation enables independent optimization of each core's operating parameters while maintaining system reliability.
Solution Approach 2:
The patent implements local quality control by determining and applying individual Vdd-frequency characteristics for each core. Each core receives customized voltage and frequency settings based on its regional technology variability, allowing faster cores to operate at higher frequencies while slower cores operate at appropriate lower frequencies. This local optimization resolves the contradiction between maintaining reliable operation across all cores and maximizing overall system performance.
2Productivity
If individual Vdd-frequency characteristics are determined and applied to each core, then performance is improved by allowing faster cores to operate at higher frequencies, but device complexity increases due to additional control mechanisms
Solution Approach 1:
The patent applies preliminary action by determining the Vdd-frequency characteristics for each core during manufacturing or initialization. These characteristics are stored and used to pre-configured optimal operating parameters for each core. This preliminary characterization eliminates the need for complex real-time optimization algorithms during operation, reducing operational complexity while maintaining performance benefits.
Solution Approach 2:
The patent implements feedback mechanisms through error detection circuitry that monitors core operation and provides information about actual performance. This feedback is used to verify that cores are operating within their valid regions and to adjust parameters as needed. The feedback system simplifies control by using direct performance measurements rather than complex predictive models.
Data Source
AI summary
A method of optimizing performance of a multi-core chip having a plurality of cores includes the steps of determining a Vdd-frequency SCHMOO characteristic for each of the plurality of cores individually; saving data indicative of the Vdd-frequency SCHMOO characteristics for each of the plurality of cores; configuring the cores to obtain a configuration providing at least one of optimum power consumption and optimum performance, for a given workload, based on the saved data; and saving the configuration such that it may be updated and used on at least one of a periodic and a continual basis.