Multi-cut Via Layout Method for Semiconductor IC Reliability
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Solution Overview
Problem
The miniaturization of semiconductor integrated circuits has made it challenging to form single-cut vias with desired patterns, leading to open faults, increased signal wiring delay, and high disconnection probabilities due to electromigration, which reduces yield and operational reliability.
Innovation Solution
A layout method for semiconductor integrated circuits that searches for and uses multi-cut via routes from the beginning of the layout process, eliminating the need for redundant via formation and improving the usage rate of multi-cut vias, thereby enhancing yield and operational reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If single-cut via is used for connection between wiring layers, then wiring density is improved, but manufacturing precision deteriorates due to difficulty in forming desired patterns
Solution Approach 1:
The via connection is segmented from a single-cut via into multiple vias (multi-cut via structure). Instead of forming one via at a location, multiple vias are formed in parallel, which divides the connection function into separate elements that are easier to manufacture with desired precision while maintaining high wiring density.
Solution Approach 2:
The via structure is made non-uniform by introducing multi-cut vias at specific locations where high reliability is needed. The local quality changes from uniform single-cut vias to selective multi-cut vias based on wiring importance, allowing precise control of manufacturing difficulty at critical locations while maintaining overall wiring density.
2Length of moving object
If single-cut via size is reduced for miniaturization, then wiring width is reduced, but reliability deteriorates due to increased open fault probability
Solution Approach 1:
The via connection function is segmented into multiple parallel vias (multi-cut via). This segmentation allows each individual via to be smaller for miniaturization while the collective group maintains high reliability through redundancy. If one via fails, others can compensate, preventing open faults.
Solution Approach 2:
The multi-cut via structure provides beforehand cushioning against open faults by creating redundant connection paths. Before a fault can occur, the system already has multiple parallel vias that can compensate if one fails, thus cushioning against reliability deterioration while allowing smaller via dimensions.
3Device complexity
If single-cut via is used, then device complexity is reduced, but operational reliability deteriorates due to increased electromigration disconnection probability
Solution Approach 1:
The via structure is segmented into multiple parallel vias instead of a single via. This segmentation increases redundancy to combat electromigration effects, where current through multiple smaller vias is less prone to causing disconnection than through one large via, while the added structural complexity is localized and manageable.
Solution Approach 2:
The via structure parameters are changed from single-cut to multi-cut configuration. This parameter change increases the number of connection paths and alters the current distribution, reducing electromigration stress on individual vias and improving operational reliability without requiring fundamental redesign of the wiring system.
4Reliability
If redundant via is added after layout to improve reliability, then via connection reliability is improved, but device complexity increases and some locations cannot accommodate redundant vias
Solution Approach 1:
The multi-cut via structure is implemented as a preliminary action during the initial layout phase rather than adding redundant vias afterward. This preliminary incorporation of multiple vias in the design stage allows for systematic planning of via locations and patterns, avoiding the need for post-layout modifications and reducing the complexity increase that would result from retroactive changes.
Solution Approach 2:
Instead of adding redundant vias to single-cut via locations after layout (the conventional approach), the invention inverts the approach by directly designing multi-cut via structures from the beginning. This reversal eliminates the need for post-layout via addition and the associated complexity increases, while still achieving the reliability benefits of redundant via connections.
Data Source
AI summary
The present invention is a method that a redundant via is never added afterwards for a signal wiring or a clock wiring, but layout is performed using a multi-cut via from the beginning, which is used for laying out a semiconductor integrated circuit by a step (S32) of searching a wiring route that layout is possible using a multi-cut via regarding a net in a net list, a step (S33) of laying out a wiring corresponding to the net on the wiring route with using the multi-cut via, and a step (S70) of creating layout data of the semiconductor integrated circuit by repeating the steps S32 and S33.