Multicycle Path Clock Control for At-Speed Circuit Testing
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Solution Overview
Problem
Existing automatic test pattern generator (ATPG) tools are unable to test multicycle path circuits effectively, as they only support circuits accessible within one clock cycle, leading to undetected defective multicycle path circuits and reduced chip yield.
Innovation Solution
A multicycle path circuit with an on-chip clock controller that provides clock signals in a multicycle phase relationship, allowing the circuit to operate in both functional and at-speed test modes, ensuring consistent clock paths and avoiding timing conflicts, and utilizing pulse shapers and multiplexers to manage clock signals for testing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If existing ATPG tools are used to test circuits, then testing can be performed within one clock cycle, but multicycle path circuits cannot be tested effectively leading to undetected defects
Solution Approach 1:
The patent introduces a dual-mode operational system that dynamically switches between functional mode (normal operation) and at-speed test mode (testing operation). The clock controller and pulse shapers dynamically adjust clock signal generation based on the operational mode, enabling the circuit to adapt its behavior for specific testing purposes while maintaining normal functionality during regular operation.
Solution Approach 2:
The patent segments the testing process into distinct phases by separating functional operation from test operation. The test mode captures signals at specific clock cycle transitions (e.g., rising edge to falling edge) rather than continuously, allowing multicycle path testing to be broken down into manageable capture points that can be analyzed separately.
2Reliability
If clock signals are provided to first and second circuits in multicycle phase relationship, then at-speed testing of multicycle path circuits is enabled, but hold and setup timing conflicts may occur
Solution Approach 1:
The patent introduces pulse shapers as intermediary components between the clock controller and the first/second circuits. These pulse shapers condition and format the clock signals before delivery, ensuring that clock transitions occur at precisely controlled times that avoid setup and hold time violations. The pulse shapers act as buffers that mediate the timing relationship between master and slave circuits.
Solution Approach 2:
The patent performs preliminary timing analysis and clock signal conditioning before actual testing occurs. The clock controller pre-configures the multicycle phase relationship and the pulse shapers pre-condition the clock signals to ensure proper timing margins are established before data capture begins, preventing timing conflicts before they can occur during testing.
3Adaptability or versatility
If the circuit operates in both functional mode and at-speed test mode, then comprehensive testing is achieved, but clock path consistency must be maintained across modes
Solution Approach 1:
The patent implements a universal clock distribution architecture where the same clock controller and pulse shaper components serve both functional mode and at-speed test mode operations. The clock paths are designed to be mode-agnostic, with the same physical routes used for clock distribution regardless of operational mode, ensuring timing characteristics remain consistent while the functional behavior changes based on mode selection.
Data Source
AI summary
A multicycle path circuit capable of operating at a functional mode and an at-speed test mode. The multicycle path circuit includes an on-chip controller configured to receive an on-chip clock signal and modulate the on-chip clock signal to provide a first clock signal to a first circuit and a second clock signal to a second circuit. The first clock signal and the second clock signal are in a multicycle phase relationship. The on-chip controller is configured to ensure the clock paths to and from the second circuit to be the same for the functional mode and the at-speed test mode and therefore to avoid hold and setup timing conflict between these modes.