Multi-Cycle Rule Scheduling in Synchronous Digital Systems
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Solution Overview
Problem
Existing circuit synthesis methods face challenges in efficiently scheduling multi-cycle rules in synchronous digital systems, which limits the clock rate and requires substantial circuitry, making it difficult to modify timing characteristics without affecting functionality.
Innovation Solution
The method involves using signal triples to implement multi-cycle circuits, allowing for variable execution times by introducing or removing delay registers without altering the system's functionality, and scheduling multiple multi-cycle rules in a single clock cycle using a scheduler that selects rules based on guard values, enabling efficient timing analysis and optimization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If traditional single-cycle rule scheduling is used in synchronous digital systems, then the circuit implementation is straightforward, but the clock rate is limited and substantial circuitry is required
Solution Approach 1:
The patent applies dynamics by making the circuit execution time variable rather than fixed. Multi-cycle rules allow different rules to execute for different numbers of clock cycles based on their specific requirements. The scheduler dynamically determines the execution duration of each rule, enabling the system to optimize clock rate by allowing critical paths to execute over multiple cycles while non-critical paths complete in fewer cycles, thus resolving the contradiction between speed and complexity
Solution Approach 2:
The patent segments the execution timeline into multiple clock cycles, allowing different rules to be scheduled in different cycles. This segmentation enables the system to handle multi-cycle rules by breaking down their execution across multiple time slots, while the scheduler manages the allocation of cycles to different rules, reducing overall circuit complexity by avoiding the need for all rules to complete in a single cycle
2Adaptability or versatility
If multi-cycle rules are implemented with fixed timing, then the circuit functionality is determined, but timing characteristics cannot be modified without affecting functionality
Solution Approach 1:
The patent makes timing characteristics dynamic and modifiable by introducing delay registers that can be inserted or removed from signal paths. The scheduler is designed to maintain functional correctness regardless of timing variations, allowing the system to adapt timing characteristics for optimization while preserving the reliability of the underlying functionality through the guard-based scheduling mechanism
Solution Approach 2:
The patent applies parameter changes by allowing modification of timing parameters (such as delay register insertion) without changing the functional parameters of the system. The scheduler abstracts the timing details from the functional logic, enabling independent adjustment of timing characteristics while maintaining functional correctness through the invariant guard conditions that dictate rule execution
3Productivity
If multiple multi-cycle rules are scheduled in a single clock cycle, then productivity increases, but scheduling complexity increases
Solution Approach 1:
The patent introduces a scheduler as an intermediary component that manages the complex task of coordinating multiple multi-cycle rules. The scheduler acts as a mediator between the rule definitions and the execution machinery, handling the complexity of determining which rules can execute concurrently and for how many cycles. This intermediary approach enables high productivity by allowing multiple rules to execute in parallel while containing scheduling complexity in a dedicated component rather than distributing it throughout the entire system
Data Source
AI summary
Enabling scheduling of single cycle as well as scheduling multi-cycle rules in a synchronous digital system whose behavior is governed by an asynchronous system specification (e.g., a TRS) provides a way to allow complex actions at state transitions of the asynchronous system without requiring that the complex actions be synthesized in logic that must be performed in a single clock cycle. For example, a relatively infrequent action may include a critical timing path that determines the maximum clock frequency of the system. By allowing that infrequent action to take multiple clock cycles, even if that action takes more absolute time, other actions may take less absolute time by virtue of being able to operate the synchronous system at a higher clock rate. The overall system may then operate more quickly (e.g., as measured by the average number of rules applied per unit of absolute time).