Multi-Deck Conductive Feature for FinFET Interconnects

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Solution Overview

Problem

The semiconductor industry faces challenges in scaling planar devices, particularly with non-planar transistors like FinFETs, due to issues such as short-channel effects, current leakage, and interconnect structure resistance, especially in metal filling and contact resistance, which conventional conductive features struggle to address effectively.

Innovation Solution

A semiconductor device structure and method that includes a multi-deck conductive feature with a bottom metal feature of cobalt and a top metal feature of copper, separated by a barrier layer and a liner, which enhances adhesion, barrier effects, and gap filling, reducing resistance and improving conductivity in the interconnect structure.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional single-deck conductive features are used, then the structure is simple, but the resistance is high and gap filling is poor

Engineering Contradiction:
ImproveconductivityVSAvoidconductive feature structure
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The conductive feature is divided into multiple decks (first deck, second deck, third deck) with different metal materials. Each deck can be independently optimized for specific functions: lower decks use metals with good gap filling (e.g., cobalt), upper decks use metals with low resistance (e.g., copper). This segmentation resolves the contradiction by allowing complex multi-material structure to achieve better conductivity and gap filling performance.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent employs composite metal structures where different metal materials are combined in a multi-deck configuration. Each deck uses metals selected based on their specific properties: some metals provide excellent gap filling capability while others provide low resistance. This composite approach allows the conductive feature to simultaneously achieve good gap filling and low resistance, resolving the technical contradiction between reliability and structural complexity.

Inventive Principle:
Principle #40Composite materials

2Productivity

If contact hole dimensions are reduced, then the interconnect density increases, but the contact resistance increases

Engineering Contradiction:
Improveinterconnect densityVSAvoidcontact resistance
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

Different metal materials are assigned to different decks based on their local functional requirements. Lower decks that interface with contact holes use metals with superior gap filling properties to ensure complete filling of reduced-dimension holes, while upper decks use low-resistance metals to minimize overall resistance. This local optimization resolves the contradiction between increased interconnect density and maintained contact resistance.

Inventive Principle:
Principle #3Local quality

3Length of stationary object

If barrier layer dimensions are reduced, then the contact hole size decreases, but the metal filling becomes more difficult

Engineering Contradiction:
Improvecontact hole sizeVSAvoidmetal filling
Core Design Contradiction:
Length of stationary objectVSEase of manufacture

Solution Approach 1:

The conductive feature is segmented into multiple decks where lower decks use metals specifically selected for their gap filling capability to fill the contact holes formed by reduced barrier layers. This segmentation allows the manufacturing process to overcome the difficulty of filling small contact holes by using materials with appropriate wetting and filling properties in the lower decks, while upper decks use low-resistance metals.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS20220367663A1Interconnect structure having a multi-deck conductive feature and method of forming the same
Publication Date: 2022.11.17 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US20220367663A1 patent drawing
  • US20220367663A1 patent drawing
  • US20220367663A1 patent drawing

AI summary

The present disclosure provides a semiconductor device structure that includes: a fin active region extruded above a semiconductor substrate; a gate stack disposed on the fin active region, wherein the gate stack includes a gate dielectric layer and a gate electrode; source/drain (S/D) features formed on the fin active region and interposed by the gate stack; and a conductive feature electrically connected to the gate electrode or the S/D features. The conductive feature includes a bottom metal feature of a first metal; a top metal feature of a second metal over the bottom metal feature, wherein the second metal is different from the first metal in composition; a barrier layer surrounding both the top metal feature and the bottom metal feature; and a liner surrounding both the top metal feature and separating the top metal feature from the bottom metal feature and the barrier layer.