Multi-Decoder Bitstream Partitioning for SoC Video Decoding
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Solution Overview
Problem
Existing video decoding systems face challenges in efficiently decoding high-definition video streams due to data path congestion caused by data sharing between multi-cores in a System on Chip (SoC) architecture.
Innovation Solution
A decoding device and method that classify bitstreams into multiple streams based on blocks defined by a matrix within a frame, utilizing multiple decoders and buffers to manage and store decoding data, thereby reducing data path congestion by controlling memory access and data transmission between processors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If multiple decoders share common memory in an SoC architecture, then device complexity is reduced, but data path congestion increases due to frequent data access between multi-cores
Solution Approach 1:
The patent divides the frame into multiple blocks arranged in a matrix and classifies them into different bitstreams based on their positions. Each decoder processes specific bitstreams, segmenting the decoding workload. This segmentation reduces data path congestion by distributing memory access patterns across multiple decoders, thereby improving decoding speed while maintaining the shared memory architecture.
2Productivity
If bitstream classification and multi-decoder architecture are implemented, then data path congestion is reduced, but device complexity increases due to additional memory and buffer management
Solution Approach 1:
The patent combines multiple decoders, memories, and buffers into an integrated SoC architecture. The first decoder includes a first processor and first memory, while the second decoder includes a second processor and second memory. This merging approach achieves parallel processing capability to improve decoding speed while consolidating components to manage complexity through systematic organization rather than separate discrete systems.
Solution Approach 2:
The patent introduces buffers as intermediary components between decoders and memories. The first buffer transmits decoding data between the first processor and second memory, while the second buffer transmits between the second processor and first memory. These buffers act as mediators that manage data flow and reduce direct access congestion between multi-cores and shared memory, improving decoding speed while maintaining manageable system complexity.
3Adaptability or versatility
If cross-memory data transmission is implemented between decoders, then data sharing efficiency is improved, but data path congestion increases due to additional data access paths
Solution Approach 1:
The patent implements preliminary classification of bitstreams into first and second bitstreams based on block positions in the frame before decoding. This preliminary action organizes data in advance to enable efficient cross-memory transmission. The first decoder processes first bitstream and can store results in second memory, while the second decoder processes second bitstream and can store results in first memory, reducing congestion by pre-organizing data flow patterns.
Data Source
AI summary
A decoding device includes a controller classifying a bitstream as a first bitstream and a second bitstream based on a plurality of blocks defined by a matrix and included in a frame, a first decoder including a first processor performing decoding on the first bitstream and outputting first decoding data and a first memory, a second decoder including a second processor performing decoding on the second bitstream and outputting second decoding data and a second memory, a first buffer transmitting the first decoding data to the second memory, and a second buffer transmitting the second decoding data to the first memory. The first processor controls the second memory to store the first decoding data, and the second processor controls the first memory to store the second decoding data.