Multi-Die Clocking Architecture for Chiplet Skew Reduction
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Solution Overview
Problem
In multi-die packages, clock skew between chiplets due to separate PLL operations leads to latency and performance degradation, especially when crossing clock domains.
Innovation Solution
A system PLL circuit receives a primary reference clock and generates identical or adjusted reference clocks, which are then distributed to PLL circuits within the package, ensuring synchronized sub-reference clocks for chiplets, thereby reducing skew and improving synchronization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If separate PLL circuits are used for each chiplet, then each chiplet can have independent clock generation, but clock skew is introduced between chiplets
Solution Approach 1:
The patent merges the clock generation function by introducing a system PLL circuit that provides a common reference clock to all chiplet PLL circuits. This unified approach maintains independent clock generation capability for each chiplet while eliminating skew through a shared reference source, directly resolving the contradiction between adaptability and precision.
Solution Approach 2:
The system PLL circuit acts as an intermediary between the external reference clock and the individual chiplet PLL circuits. It receives the external reference clock and distributes synchronized reference clocks to all chiplets, mediating the clock distribution to eliminate skew while preserving independent operation.
2Ease of operation
If separate PLL operations are used for each chiplet, then local clock signals can be provided, but latency and performance degradation occur due to skew
Solution Approach 1:
By merging the reference clock distribution through a system PLL, the patent eliminates the performance-degrading skew while maintaining the ease of local clock provision. Each chiplet continues to receive local clock signals from its own PLL, but the reference input is now synchronized across all chiplets.
3Adaptability or versatility
If multiple PLL circuits are used across chiplets, then sub-reference clocks can be generated, but synchronization difficulties arise
Solution Approach 1:
The system PLL serves as a mediator that receives a single external reference clock and distributes identical reference clocks to all chiplet PLL circuits. This ensures that all sub-reference clocks are derived from the same synchronized source, eliminating synchronization issues while preserving the ability to generate multiple sub-reference frequencies.
Data Source
AI summary
A device including a system phase lock loop circuit to: receive a primary reference clock, generate a reference clock from the primary reference clock, and transmit the reference clock; and a phase lock loop circuit to receive the reference clocks, generate a sub-reference clock from the received respective reference clocks, and transmit the sub-reference clock from the phase lock loop circuit to drive operation of a first chiplet using the respective sub-reference clock, wherein the sub-reference clock drives the first chiplet.