Multi-Die IC Inter-Die Connection Testing via Programmable Micro-Bump Routing
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Solution Overview
Problem
The challenge in testing and identifying faulty inter-die connections in multi-die integrated circuits (ICs) becomes more significant as die size increases, leading to higher costs and reduced yield due to the larger number of inter-die connections, which are often not independently tested in conventional multi-die ICs.
Innovation Solution
The proposed solution involves a method for testing inter-die connections in multi-die ICs using programmable circuitry to establish internal connections between micro-bumps and TSVs, with probe pads and package bumps facilitating the testing of signal propagation, allowing for the identification of faulty connections and reprocessing or permanent bonding based on test results.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multi-die ICs are used to reduce manufacturing flaws and increase yield, then the probability of flaws in individual dies decreases, but the complexity of testing inter-die connections increases
Solution Approach 1:
The patent segments the testing process into two distinct phases: a first test performed before permanent bonding to identify faulty inter-die connections, and a second test after bonding to verify final functionality. This segmentation allows complex testing to be managed in manageable stages, testing individual dies separately before assembly, thereby reducing overall testing complexity while maintaining high reliability
Solution Approach 2:
The patent performs preliminary testing of inter-die connections before permanent bonding of dies. By conducting tests on micro-bumps and inter-die connections prior to final assembly, faulty connections can be identified and corrected in advance, preventing waste of expensive permanently bonded dies and reducing the complexity of post-bonding repairs
2Reliability
If thorough testing of inter-die connections is performed to ensure reliability, then connection robustness improves, but manufacturing cost increases
Solution Approach 1:
The patent implements preliminary testing of inter-die connections through micro-bumps before permanent die bonding. This early detection capability allows faulty connections to be identified and reworked while dies are still accessible, avoiding the cost of discarding expensive permanently bonded dies with hidden defects, thereby improving connection robustness without proportionally increasing manufacturing cost
Solution Approach 2:
The patent employs self-test circuitry embedded within each die that automatically tests inter-die connections without requiring external testing equipment. This self-service approach reduces manufacturing cost by eliminating complex external testing apparatus while ensuring thorough testing of connection robustness through internally generated test patterns and evaluation logic
3Reliability
If larger dies are used to implement ICs, then the number of manufacturing flaws decreases per die, but the number of inter-die connections increases
Solution Approach 1:
The patent segments the large die into multiple smaller dies, each with fewer internal flaws, while systematically managing the resulting inter-die connections through structured test circuits. The segmentation principle is applied both to dividing the functional circuitry across multiple dies and to dividing the testing process into manageable phases, thereby reducing flaw probability in individual dies while controlling the complexity of inter-die connections through organized test approaches
Solution Approach 2:
The patent implements universal test circuitry that can test multiple types of inter-die connections (micro-bumps, TSVs, wire bonds) using the same basic test architecture. This multi-functional test system handles various connection types and testing scenarios through configurable test patterns and reusable test logic, reducing the complexity increase that would otherwise result from testing diverse inter-die connection structures
Data Source
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AI summary
An integrated circuit (100) includes a first die (105, 110), a second die (115) on which the first die may be disposed, a plurality of inter-die connections (205, 205A, 205B) coupling the first die to the second die, and a plurality of probe pads (120, 120A, 120B, 120C, 120D, 120E), where each probe pad is coupled (305, 310, 405, 410) to at least one of the inter-die connections. The first die may be configured to establish an internal connection (315, 415, 420, 515) coupling the first probe pad to the second probe pad. In some embodiments, each probe pad is coupled to a micro-bump (210), and the internal connections couple the micro-bumps one to another. Some embodiments utilize through silicon vias extending through the second die. Methods of testing the described integrated circuits are also disclosed.