Multi-Die IC Partitioning via Timing and Cut Cost Optimization
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In multi-die integrated circuits, existing partitioning methods often violate timing constraints or exceed the limited number of available inter-die conductive structures, making it challenging to efficiently allocate circuit elements across dies.
Innovation Solution
A method that determines target area and cut utilizations by iterating over timing violations, calculating a partition cost that accounts for cut size, timing, and area utilization, and assigns circuit elements to partitions based on these constraints to minimize violations and optimize resource use.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If circuit elements are allocated to minimize timing violations, then timing constraints are improved, but the number of inter-die conductive structures required increases
Solution Approach 1:
The patent changes the parameters of the partitioning algorithm by introducing a cost function that incorporates both timing violations and cut size (number of inter-die conductive structures). The algorithm iterates over different timing violation thresholds and adjusts partitioning decisions based on a calculated cost that balances timing constraint satisfaction with the number of conductive structures required, rather than minimizing either parameter independently
Solution Approach 2:
The patent employs a dynamic partitioning approach where the allocation of circuit elements to dies is adjusted based on iterative evaluation of timing violations and conductive structure usage. The system dynamically modifies partitioning decisions by considering both timing constraints and the limited availability of inter-die conductive structures, adapting the solution to satisfy multiple constraints simultaneously
2Reliability
If more inter-die conductive structures are used to satisfy timing constraints, then timing violations are reduced, but the available conductive structures are exceeded
Solution Approach 1:
The patent modifies the partitioning optimization by using a cost function that penalizes both timing violations and excessive use of inter-die conductive structures. The algorithm iterates through different timing violation thresholds and adjusts the partitioning to achieve an optimal balance, changing the parameters of the optimization problem to include both timing and conductive structure constraints
Solution Approach 2:
The patent applies partial action by not attempting to eliminate all timing violations or fully utilize all available conductive structures, but rather achieving an optimal balance where the cost of additional conductive structures is justified by the reduction in timing violations. The iterative process determines the point of diminishing returns for each parameter
3Quantity of substance
If circuit design is partitioned to fit available conductive structures, then resource utilization is improved, but timing constraints are violated
Solution Approach 1:
The patent changes the optimization parameters by using a cost function that weighs both conductive structure utilization and timing constraint satisfaction. The algorithm iterates over different timing violation thresholds and adjusts the partitioning decisions accordingly, rather than fixing one parameter and optimizing the other independently
Solution Approach 2:
The patent employs a dynamic optimization process where the partitioning solution is continuously adjusted based on both the available conductive structures and the timing constraints. The system dynamically re-evaluates partitioning decisions to achieve an optimal balance between resource utilization and timing satisfaction
4Productivity
If iterative optimization is performed to find optimal partitioning, then partition cost is minimized, but computation time increases
Solution Approach 1:
The patent applies partial action by implementing a limited iterative optimization process that performs a sufficient number of iterations to achieve a good partitioning solution without exhausting all possible computational time. The algorithm iterates over a range of timing violation thresholds and stops when further iterations yield diminishing improvements in partition cost
Data Source
AI summary
Partitioning a circuit design can include determining, using a processor, a target area utilization and a target cut utilization by iterating over a range of timing violations and determining, using the processor, a worst allowed timing violation based upon the target area utilization and the target cut utilization. Circuit elements of the circuit design can be assigned to partitions, using the processor, for implementation of the circuit design in a multi-die integrated circuit based upon a partition cost calculated using the target area utilization, the target cut utilization, and the worst allowed timing violation.