Multi-Die IC Variation Reduction via Performance Metric Sorting
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Solution Overview
Problem
As the size of integrated circuits (ICs) increases, the likelihood of manufacturing flaws also increases, leading to reduced operability or complete failure, making it more cost-effective to implement ICs as multi-die structures rather than single, monolithic dies, where a fault in one die renders only that die inoperable, thus minimizing unusable die area.
Innovation Solution
A method and system for reducing variation in multi-die ICs by determining performance metrics for each die and interposer, sorting them into groups, and selecting dies and interposers based on these metrics to ensure the multi-die IC meets performance specifications, such as static power dissipation and operating frequency, thereby avoiding the inclusion of substandard dies that could degrade overall performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a single, monolithic die is used to implement an IC, then the IC can achieve high performance, but the probability of manufacturing flaws increases and the cost-effectiveness decreases
Solution Approach 1:
The patent divides a large integrated circuit into multiple smaller dies that are coupled together in a multi-die configuration. Each die is smaller and less prone to manufacturing flaws, yet collectively they implement the full IC functionality. This segmentation reduces the probability of manufacturing flaws while maintaining the required performance through inter-die interconnects.
2Productivity
If a single, monolithic die is used to implement an IC, then the IC can achieve high performance, but the cost-effectiveness decreases
Solution Approach 1:
The patent segments the IC into multiple smaller dies, which reduces manufacturing flaw probability and improves cost-effectiveness. Smaller dies have lower yields issues and can be manufactured more reliably, reducing the cost of rework and replacement while maintaining productivity.
3Reliability
If multiple dies are coupled together to form a multi-die IC, then the manufacturing flaw impact is minimized, but the variation in performance metrics increases
Solution Approach 1:
The patent applies preliminary action by sorting and selecting dies based on performance metrics before coupling them into a multi-die IC. Dies are characterized and grouped according to their performance characteristics, ensuring that only compatible dies with minimal variation are assembled together. This pre-screening process reduces performance metric variation in the final multi-die IC while maintaining the fault tolerance benefits of the multi-die architecture.
Data Source
AI summary
A method of reducing variation in multi-die integrated circuits can include, for each of a plurality of dies, determining at least one performance metric and selecting at least two dies for inclusion within a multi-die integrated circuit according to the at least one performance metric. Systems and devices for executing the steps of the method are also described.