Multi-Die IC Interposer At-Speed Testing via Loop-Back Paths
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Integrated circuits (ICs) face challenges in testing wires for defects such as high resistance or delay issues, which can go undetected even if the wires pass signals, as existing testing methods are not effective in identifying these defects at operational speeds.
Innovation Solution
The implementation of a multi-die IC structure with an interposer and programmable die, where inter-die wires are tested using loop-back paths and scan chain circuitry to propagate test signals, allowing for automated at-speed testing of inter-die wires and estimation of resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If existing testing methods are used to test inter-die wires, then the testing process is simple, but defects such as high resistance or delay issues cannot be detected
Solution Approach 1:
The testing system is segmented into multiple functional components: a test signal generator, an interposer with test structures, and a response analyzer. Each component performs a specific function in the defect detection process, allowing complex testing capabilities to be achieved through modular assembly rather than a monolithic complex system.
Solution Approach 2:
The interposer serves as an intermediary structure between the first die and second die, providing dedicated test signal paths and loop-back mechanisms. This intermediary component enables defect detection in inter-die wires without requiring direct access to the wires themselves, simplifying the overall testing architecture while maintaining high detection reliability.
2Measurement precision
If wires are tested at operational speeds, then testing accuracy improves, but testing complexity and equipment requirements increase
Solution Approach 1:
Test structures including flip-flops and loop-back paths are built into the IC design during manufacturing, before the actual testing occurs. This preliminary preparation of test infrastructure allows operational-speed testing to be performed without requiring external complex testing equipment, as the test paths are already embedded in the device architecture.
Solution Approach 2:
The IC structure performs self-testing by utilizing its own internal circuitry (flip-flops, inter-die wires, and loop-back paths) to propagate and detect test signals. The device tests itself at operational speeds without requiring external testing equipment, thereby achieving high measurement precision while avoiding the complexity of specialized test equipment.
3Productivity
If automated testing is implemented, then productivity increases, but device complexity increases
Solution Approach 1:
The test signal paths and loop-back structures serve multiple functions: they enable automated testing, provide defect detection capabilities, and can be configured to test different wire pairs through sequential circuit designs. This multi-functionality allows a single testing infrastructure to handle various testing scenarios, increasing productivity without proportionally increasing complexity.
Data Source
AI summary
An integrated circuit (IC) structure can include an interposer including a plurality of inter-die wires and a first die coupled to the interposer. The first die can include a first output including a first flip-flop coupled to a first inter-die wire of the plurality of inter-die wires and a first input including a second flip-flop coupled to a second inter-die wire of the plurality of inter-die wires. The IC structure can include a second die coupled to the interposer. The second die can be configured with a first circuit design forming circuitry that couples the first inter-die wire to the second inter-die wire.