Multi-Die Semiconductor Package Layout for CTE Stress Relief
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Solution Overview
Problem
Conventional semiconductor packaging technologies face challenges in reducing thermal stress and improving heat dissipation efficiency due to coefficient of thermal expansion (CTE) mismatches between materials, which can lead to delamination and reliability issues.
Innovation Solution
A semiconductor package is formed with an organic interposer and a conductive layer that fills gaps between dies and covers their back surfaces, using an underfill material with a higher CTE than the encapsulating material to minimize CTE mismatch and enhance heat dissipation, while the encapsulating material is kept from filling these gaps to prevent delamination.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If encapsulating material fills the gaps between dies, then complete encapsulation is achieved, but thermal stress increases and delamination risk occurs due to CTE mismatch
Solution Approach 1:
The patent applies local quality by using different materials with different CTE values in different locations: the underfill material (with CTE of 50-80 ppm/°C) is placed in the gaps between dies, while the encapsulating material (with lower CTE) is used for overall encapsulation. This local differentiation allows the underfill to compensate for thermal expansion differences at the critical interface between dies and encapsulating material, reducing thermal stress and preventing delamination.
Solution Approach 2:
The underfill material serves as an intermediary between the dies and the encapsulating material. It acts as a buffer layer that absorbs thermal expansion mismatches, protecting the die-encapsulating material interface from stress. The underfill's higher CTE allows it to expand more with temperature changes, compensating for the rigid encapsulating material and preventing delamination.
2Loss of energy
If conventional packaging materials are used, then manufacturing simplicity is maintained, but heat dissipation efficiency is insufficient due to CTE mismatch and thermal stress
Solution Approach 1:
The patent changes the CTE parameter of the material in the gap region by selecting underfill material with specifically higher CTE (50-80 ppm/°C) compared to the encapsulating material. This parameter change allows the material to better match thermal expansion characteristics of the dies, reducing thermal stress and improving heat dissipation efficiency while maintaining package reliability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution reduces the risk of delamination and improves the reliability and heat dissipation efficiency of the semiconductor package by managing thermal stress and material compatibility.
Implementation Method 1
an underfill filling between the interconnect structure and the plurality of dies and filling a lower part of a gap between adjacent two of the plurality of dies, wherein the underfill has a higher coefficient of thermal expansion than the encapsulating material
Data Source
AI summary
A semiconductor package includes an interconnect structure, a plurality of dies disposed on the interconnect structure in a side-by-side manner, an underfill filling between the interconnect structure and the plurality of dies and filling a lower part of a gap between adjacent two of the plurality of dies, a conductive layer at least covering back surfaces of the adjacent two of the plurality of dies and filling an upper part of the gap, and an encapsulating material laterally encapsulating the plurality of dies and the conductive layer.