Multi-dimensional Cache Architecture for 3D NoC Latency
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Solution Overview
Problem
Conventional 3D Network-on-Chip (NoC) designs face challenges in reducing traffic latency and incorporating 3D architecture due to router logic complexity and thermal limitations, as they often rely on synthetic traffic generation and assume stacked processing elements without practical full system designs.
Innovation Solution
The implementation of a multi-dimensional cache memory scheme with 3D interconnect logic, which adds a vertical Z-direction to a coherent mesh network using 3D router logic, distributes traffic injection throughout the 3D NoC and interleaves L2 cache sets across multiple layers, simplifying router logic and protocols, and leveraging multiple 2D mesh networks to achieve benefits of 3D NoC without the complexity of 3D routing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If 3D router logic is added to a mesh network to enable 3D NoC architecture, then traffic latency is reduced and capacity is increased, but router logic complexity and routing latency increase
Solution Approach 1:
The patent applies dimensionality change by transitioning from a conventional 2D mesh network to a 3D NoC architecture, adding a vertical Z-dimension to the network topology. This enables traffic to be routed through multiple layers stacked vertically, reducing the number of hops required for data transmission and thereby decreasing latency while increasing overall network capacity.
Solution Approach 2:
The patent segments the mesh network into multiple 2D mesh layers stacked vertically in the Z-dimension. Each layer can be independently routed, allowing traffic to be distributed across multiple parallel paths. This segmentation reduces the complexity of any single router while maintaining the benefits of 3D architecture through layered decomposition.
2Productivity
If processing elements are stacked in 3D to increase density, then integration is improved, but thermal limitations worsen
Solution Approach 1:
The patent utilizes the vertical Z-dimension for stacking cache layers and processing elements, enabling high integration density by moving from a planar 2D arrangement to a three-dimensional stacked architecture. This vertical integration allows multiple functional layers to coexist without increasing the chip footprint.
Solution Approach 2:
The patent segments the system into distinct functional layers (e.g., cache layers, processing layers) stacked vertically. This layering separates heat-generating computational elements from cache memory, improving thermal management by distributing heat sources across multiple layers rather than concentrating them in a single plane.
3Quantity of substance
If L2 cache sets are interleaved across multiple layers, then capacity is increased and traffic is distributed, but inter-layer data links are required
Solution Approach 1:
The patent interleaves L2 cache sets across multiple vertical layers in the Z-dimension, distributing cache capacity throughout the stacked architecture. This vertical distribution increases total cache capacity and spreads traffic load across multiple layers, preventing any single layer from becoming a bottleneck.
Solution Approach 2:
The inter-layer data links serve multiple functions: they enable cache access across layers, provide routing paths for NoC traffic, and support both read and write operations. This multi-functionality reduces the need for dedicated specialized connections for each purpose.
Data Source
AI summary
Various implementations described herein are directed to a device with a multi-layered logic structure with multiple layers including a first layer and a second layer arranged vertically in a stacked configuration. The device may have a first cache memory with first interconnect logic disposed in the first layer. The device may have a second cache memory with second interconnect logic disposed in the second layer, wherein the second interconnect logic in the second layer is linked to the first interconnect logic in the first layer.