Multi-Dimensional SoC Architecture for Low-Latency Image Processing
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Solution Overview
Problem
Conventional processing systems experience mismatches in processing speed and data transfer speed, leading to reduced overall system performance and inability to handle complex computational processes efficiently, particularly in image processing and graphics processing.
Innovation Solution
A system-on-a-chip (SoC) architecture that includes multiple processors and a memory device, allowing for parallelized execution of image feature recognition operations across multiple dimensions, with processors like GPUs and PPEs, and utilizing vector processing units (VPUs) to maximize processor utilization and reduce redundant data loading operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional processing systems are used, then system simplicity is maintained, but processing speed and computational efficiency deteriorate due to mismatches between processing components
Solution Approach 1:
The system is divided into multiple specialized processing units (GPUs, PPEs, VPUs) that each handle specific aspects of image processing. This segmentation allows parallel execution of different processing tasks simultaneously, resolving the speed-complexity contradiction by trading structural complexity for computational throughput.
Solution Approach 2:
The patent introduces multi-dimensional data processing capabilities where frame data is processed across multiple dimensions (spatial, temporal, feature dimensions) simultaneously. This dimensional expansion enables parallel processing operations that increase speed while distributing complexity across different processing dimensions rather than concentrating it in a single sequential path.
2Productivity
If data is processed sequentially through single processors, then device complexity is reduced, but productivity and processing throughput deteriorate
Solution Approach 1:
Multiple processing units (GPUs for general parallel processing, PPEs for pixel-level operations, VPUs for vector computations) are merged into a unified system that shares common data pathways and memory interfaces. This merging enables high throughput by processing different aspects of image data simultaneously while managing complexity through shared infrastructure.
Solution Approach 2:
The processing system is designed with multi-functional capability where processors can handle various types of computational tasks (image processing, graphics processing, general-purpose computation) through standardized interfaces and instruction sets. This universality increases productivity by eliminating the need for separate specialized systems while keeping architecture complexity manageable through code reuse and standardized data formats.
3Loss of time
If frame data is loaded repeatedly for each processing operation, then processor utilization is simplified, but loss of time increases due to redundant data loading operations
Solution Approach 1:
Frame data is loaded into high-speed memory buffers before processing operations begin. The system performs preliminary data staging where complete frame data is available in advance for multiple processing operations, eliminating redundant loading time. This preliminary action trades memory management complexity for time efficiency by pre-positioning data where it can be accessed rapidly by multiple processors simultaneously.
Solution Approach 2:
High-speed memory buffers and data caches serve as intermediaries between external memory and processing units. These intermediary structures hold frame data in an accessible state for multiple processors, reducing direct memory access requirements and minimizing loading time. The intermediary memory layers manage the complexity of data distribution while providing fast access to all processing units.
4Manufacturing precision
If general-purpose processors are used, then adaptability is maintained, but manufacturing precision and processing accuracy deteriorate for specialized image processing tasks
Solution Approach 1:
Different processing units are assigned specialized functions optimized for specific types of operations (GPUs for parallel matrix operations, PPEs for pixel processing, VPUs for vector computations). This local specialization improves image feature recognition accuracy for each task type while maintaining overall system adaptability through the combination of specialized units that can handle diverse processing requirements.
Data Source
AI summary
Aspects of this technical solution can increase speed of processing in low-latency application areas, while maintaining integrity of image feature recognition at those higher speeds. For example, in image-processing environments associated with autonomous navigation (e.g., driving), a large volume of image data is to be rapidly and accurately processed to maintain reliable and up-to-date models of a physical environment. For example, embodiments in accordance with this disclosure can provide high-speed and accurate image feature recognition of input frame data beyond the capability of CPU processing or general GPU processing to achieve.