Multidimensional Turbo Product Codes for 100 Gb/s Optical BER
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Solution Overview
Problem
Current optical communication systems face significant bit-error ratio (BER) degradation due to intra-channel fiber nonlinearities, polarization mode dispersion, and chromatic dispersion, particularly at data rates above 100 Gb/s, where existing soft iteratively decodable codes are not implementable.
Innovation Solution
The implementation of multidimensional turbo product codes (MTPCs) and generalized low-density parity-check codes with component Reed-Solomon codes, operating in parallel phases for encoding and decoding, to provide a powerful forward error correction scheme suitable for beyond 100 Gb/s transmission.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If soft iteratively decodable codes (turbo-product codes and LDPC codes) are used to improve BER performance, then coding gain is improved, but implementation at data rates above 100 Gb/s becomes infeasible
Solution Approach 1:
The patent segments the coding process into multiple independent phases (first phase with ky column-encoders, second phase with nx row-encoders) that can operate in parallel. This segmentation allows the complex soft iteratively decodable codes to be broken down into manageable parallel operations that can be implemented at high data rates above 100 Gb/s while maintaining BER performance improvements.
Solution Approach 2:
The patent introduces a multidimensional structure to the turbo-product codes, transitioning from traditional two-dimensional to three-dimensional or higher-dimensional code arrays. This dimensional expansion enables additional parallel processing paths (columns, rows, and layers) that increase processing throughput to support data rates above 100 Gb/s while maintaining the iterative decoding capability for improved BER performance.
2Ease of manufacture
If standard RS(255, 239) FEC scheme is used to maintain BER quality at 40 Gb/s, then implementation is simple, but coding gain is insufficient for beyond 100 Gb/s transmission
Solution Approach 1:
The patent creates a composite coding scheme that combines Reed-Solomon component codes with turbo-product code structure. This composite approach integrates the implementation simplicity and hardware efficiency of RS codes with the superior error correction performance of iterative turbo-product codes, achieving both ease of implementation and high coding gain (at least 4 dB improvement) necessary for beyond 100 Gb/s transmission.
3Productivity
If parallel encoder/decoder phases are implemented to increase processing speed, then data rate capability is improved, but device complexity increases
Solution Approach 1:
The patent segments the parallel processing into distinct phases (first phase with ky column-encoders, second phase with nx row-encoders) that can be implemented using standardized building blocks. This segmentation reduces device complexity by reusing identical encoder/decoder modules across multiple parallel paths rather than designing entirely separate complex circuits for each path.
Solution Approach 2:
The patent designs universal encoder and decoder modules that can function in multiple roles across different phases and dimensions of the multidimensional code structure. The same basic encoder module serves as both column-encoder and row-encoder in different phases, and the decoder similarly handles both column and row decoding. This multi-functionality reduces overall device complexity while maintaining high processing speed through parallel operation.
Data Source
AI summary
A transmitter, a receiver, and corresponding methods are provided. The transmitter includes encoders configured to encode source bit streams from L information sources into bytes of codewords. Each encoder includes different (n, k) multidimensional turbo-product codes of code rate R=k/n, where k is a number of information bytes, and n is code word length. The encoders operate in at least two phases. A first phase involves operating ky column-encoders in parallel on kx bytes per column to generate the code words for a current dimension. A second phase involves operating nx row-encoders in parallel on ky memory locations per rows to generate the code words for the current dimension. The first and second phases are repeated for remaining layers of the current dimension and layers of other dimensions.