Multi-dot Flash Memory Tunnel Insulation Segmentation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current NAND flash memory technologies face challenges in miniaturization and reliability due to inter-cell interference, charge trap generation, and increased production costs, particularly in tunnel insulating films, which affect the threshold window and stability of memory cells.
Innovation Solution
A multi-dot flash memory architecture with separately provided gate and tunnel insulating films allows for controlled charge injection and emission, maintaining constant tunnel current direction to enhance reliability and reduce power consumption by gradually varying bit line potentials during writing and erasing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If the tunnel insulating film is thinned to reduce inter-cell interference, then miniaturization is improved, but charge traps are generated during writing/erasing which deteriorates reliability
Solution Approach 1:
The patent segments the insulating film structure into distinct gate insulating film and tunnel insulating film layers with different thicknesses and compositions. The gate insulating film is thicker (5-10nm) to prevent charge trap generation, while the tunnel insulating film is thinner (2-5nm) to enable efficient writing/erasing, thus resolving the contradiction between miniaturization and reliability
Solution Approach 2:
The patent employs composite material structure with multiple insulating film layers having different properties. The gate insulating film uses materials optimized for charge retention, while the tunnel insulating film uses materials optimized for charge injection/extraction, achieving both miniaturization and reliability through material composition differentiation
2Area of moving object
If the floating gate size is reduced for miniaturization, then device density is improved, but inter-cell interference increases which prevents further miniaturization
Solution Approach 1:
The patent segments the charge storage function between the thinner tunnel insulating film (for charge injection) and the thicker gate insulating film (for charge retention), allowing smaller floating gate dimensions without increasing inter-cell interference since the charge retention layer is physically separated and thicker
3Productivity
If writing/erasing operations are performed repeatedly, then data recording capacity is improved, but charge traps accumulate in the tunnel insulating film which deteriorates reliability
Solution Approach 1:
The patent segregates the writing/erasing function to the dedicated tunnel insulating film layer which can be optimized for high-speed charge injection, while the separate gate insulating film layer maintains stability and prevents charge trap accumulation from affecting overall reliability
Solution Approach 2:
The patent introduces the gate insulating film as an intermediary layer between the tunnel insulating film and the floating gate, which mediates charge retention and prevents direct exposure of the floating gate to degradation effects from repeated writing/erasing operations
4Adaptability or versatility
If the tunnel insulating film is thinned to enable random writing, then data recording flexibility is improved, but leak phenomenon increases which reduces reliability
Solution Approach 1:
The patent segments the insulating film into two functional layers: the thin tunnel insulating film enables random writing through efficient charge injection, while the thick gate insulating film acts as a barrier that prevents charge leak, thus resolving the contradiction between flexibility and reliability
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves the reliability of tunnel insulating films, maintains the threshold voltage stability, and reduces power consumption by minimizing potential variations, thus addressing the limitations of existing NAND flash memory technologies.
Implementation Method 1
a value within a range so as to prevent a transfer of electric charges due to a tunneling phenomenon
Data Source
AI summary
A multi-dot flash memory set potentials of bit lines being disposed at a left side of a selected floating gate to V2(1)>V2(2)>V2(3)> . . . and set potentials of bit lines being disposed at a right side of the selected floating gate to V1(1)<V1(2)<V1(3)< . . . . Where V2(1) is a plus potential and V1(1) is a minus potential. The potentials of the bit lines converge on 0V with being away from the selected floating gate.