Multi-Fabric Schematic Generation via Layout Parasitic Extraction
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Solution Overview
Problem
Existing methods for simulating integrated circuit (IC) designs across multiple design fabrics, such as IC, package, and printed circuit board (PCB), face challenges due to incompatible schematic formats and the difficulty in incorporating parasitic models from different design fabrics, requiring manual stitching and extensive human intervention.
Innovation Solution
A layout-driven method and system for generating a multi-fabric schematic that identifies layout connectivity and correlates devices with parasitic models, automatically instantiating parasitic models and routing them within the schematic, reducing manual effort and computational resource usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If manual creation of parasitic aware multi-fabric schematics is performed, then accuracy and correctness of parasitic model integration is improved, but time consumption and labor intensity increase significantly
Solution Approach 1:
The system automatically extracts parasitic models from layout data and integrates them into multi-fabric schematics without requiring manual intervention. The automated extraction process reads parasitic information directly from layout files and populates the schematic with appropriate models, eliminating the need for manual model integration while maintaining accuracy through systematic data extraction and validation rules
Solution Approach 2:
The manual mechanical process of stitching parasitic models into schematics is replaced by an automated computational system. The system uses software algorithms to extract parasitic data from layout files, parse the information, and automatically integrate it into the multi-fabric schematic, replacing the manual mechanical stitching process with an efficient automated digital workflow
2Adaptability or versatility
If multiple design fabrics (IC, package, PCB) are integrated into a single schematic, then system-level simulation capability is improved, but schematic complexity and difficulty of management increase
Solution Approach 1:
The multi-fabric schematic is segmented into distinct fabric-specific sections (IC fabric, package fabric, PCB fabric), each with its own parasitic model extraction rules and integration methods. This segmentation allows the system to manage complexity by treating each fabric type independently while maintaining their interconnections, making the overall system manageable through modular organization of parasitic models and connectivity information
Solution Approach 2:
The system implements a universal multi-fabric schematic framework that can handle different fabric types (IC, package, PCB) using a common integration approach. The standardized process for extracting parasitic models and integrating connectivity works across all fabric types, providing a universal solution that reduces management complexity despite the diversity of included designs
3Measurement precision
If parasitic models are extracted from combined geometries across multiple design fabrics, then accuracy of system-level parasitic analysis is improved, but computational resources and processing complexity increase
Solution Approach 1:
Parasitic models are extracted from layout geometries in advance before schematic generation. The system performs preliminary extraction of parasitic information from IC, package, and PCB layout files, storing the extracted models for later integration. This preliminary action separates the computationally intensive extraction process from the schematic generation process, allowing accurate parasitic analysis to be performed beforehand and reducing real-time computational requirements
4Productivity
If automated layout-driven schematic generation is implemented, then productivity and efficiency are improved, but requirement for automated extraction and integration systems increases
Solution Approach 1:
The system uses an intermediary device map data structure that stores the mapping relationships between layout geometries and parasitic models. This intermediary structure facilitates automated extraction by providing a standardized interface between the layout analysis process and the schematic generation process, simplifying the integration complexity while enabling high productivity through systematic data management
Data Source
AI summary
Disclosed are techniques for implementing a layout-driven, multi-fabric schematic design of an electronic design. These techniques identify a multi-fabric layout spanning across multiple design fabrics and layout connectivity information and determine a device map that correlates a first set of devices in the multi-fabric layout with respective parasitic models. The device map can be identified one or more pre-existing device maps or can be constructed anew. A multi-fabric schematic can be generated by using at least the respective parasitic models and the layout connectivity information.