Multifaceted Semiconductor Structure for Wider Gate-All-Around Channels
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Solution Overview
Problem
Conventional semiconductor devices face limitations in increasing effective transistor width without increasing the number of nanosheet channel layers or significantly raising the stack height, particularly due to the constraints of (100) nanosheet channel layers on a (100) substrate.
Innovation Solution
A semiconductor device with a substrate layer and a semiconductor structure having a protruding end formed by multiple facets, where epitaxial layer stacks are grown on these facets in an alternating manner, allowing for increased transistor width without increasing the number of layers or stack height, utilizing facets like {111} or {311} crystal facets for high-quality epitaxial growth.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If the number of nanosheet channel layers is increased to increase effective transistor width, then the effective transistor width is improved, but the sheet efficiency of the first nanosheet channel layer is reduced and the total height of the stack increases
Solution Approach 1:
The patent transitions from vertical stacking (increasing layer count in the vertical dimension) to lateral expansion (increasing channel width in the horizontal dimension). By forming layer stacks on multiple facets of a protruding semiconductor structure, the effective transistor width is increased through lateral arrangement rather than vertical stacking, thus avoiding the increase in total stack height.
2Area of moving object
If the channel widths of stacked nanosheet channel layers are increased to increase effective transistor width, then the effective transistor width is improved, but the maximum channel width is limited by the (100) substrate constraint
Solution Approach 1:
The patent changes the crystal orientation parameter from conventional (100) to alternative orientations such as (110) or (111) substrates. This parameter change enables larger channel widths and allows the formation of multiple facets on the protruding structure, providing greater flexibility in channel width design while maintaining high-quality epitaxial growth.
3Area of moving object
If layer stacks are arranged on multiple facets of a protruding semiconductor structure, then the effective transistor width is increased without increasing stack height, but the manufacturing complexity increases
Solution Approach 1:
The patent performs preliminary formation of the protruding semiconductor structure with multiple facets before arranging the layer stacks. By pre-establishing the multi-facet geometry through selective epitaxial growth or etching, the subsequent layer stack formation becomes more straightforward, as the facets are already positioned and oriented correctly for receiving the layer stacks.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the effective transistor width and device performance by enabling high-quality epitaxial growth on multiple facets, thereby improving the integrated device's performance without increasing the stack height or number of layers.
Implementation Method 1
the first layer stack may be a first epitaxial layer stack (grown with epitaxy) and the second layer stack may be a second epitaxial layer stack
Data Source
Figure 1(a)~1(b)
Figure 2
Figure 3
AI summary
This disclosure relates to semiconductor devices for integrated devices like nanosheet devices, forksheet devices, or complementary field effect transistor devices. The semiconductor device comprises a substrate layer (101, 102) and a semiconductor structure arranged partly in a trench formed in the substrate layer and partly protruding from the trench. The protruding end of the semiconductor structure is formed by at least a first and a second facet (103, 104) of the semiconductor material of the semiconductor structure, which are arranged at an angle to each other. A first layer stack (105) and a second layer stack (106) are arranged on the protruding end, each comprising one or more first semiconductor layers and one or more second semiconductor layers stacked in an alternating manner. The first layer stack is arranged on the first facet and the second layer stack is arranged on the second facet.The first and second steps may adjoin are may be separated.