Multi-Finger CMOS Electrostatic Protection Device

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Solution Overview

Problem

Traditional electrostatic protection structures for power devices have weak self-protection capabilities due to their large area, which is not suitable for applications requiring compact designs without compromising electrostatic discharge (ESD) effectiveness.

Innovation Solution

A CMOS transistor is arranged in a multi-finger-like structure with a comb-tooth-pattern active region and field oxide isolation, allowing for optimized electrostatic discharge pathways while maintaining the same distance from the polysilicon gate to contact holes, thereby reducing the device's area without compromising ESD capability.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a traditional electrostatic protection structure is used for a power device, then ESD protection capability is improved, but device area increases significantly

Engineering Contradiction:
ImproveESD protection capabilityVSAvoiddevice area
Core Design Contradiction:
ReliabilityVSArea of stationary object

Solution Approach 1:

The device channel is segmented into multiple fingers arranged in a multi-finger configuration. This segmentation allows the ESD protection functionality to be distributed across multiple smaller pathways rather than requiring a single large structure, thereby maintaining protection capability while reducing overall device area.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The invention transitions from a planar layout to a three-dimensional vertical structure by stacking source regions, drain regions, and channel regions in multiple layers. The contact holes penetrate through multiple layers to establish vertical electrical connections, effectively utilizing the vertical dimension to reduce the footprint area while maintaining the necessary L distance for ESD protection.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Reliability

If the distance L between metal contact hole and polysilicon gate is increased, then electrostatic protection capability is improved, but device area increases

Engineering Contradiction:
Improveelectrostatic protection capabilityVSAvoiddevice area
Core Design Contradiction:
ReliabilityVSArea of stationary object

Solution Approach 1:

The invention resolves this contradiction by moving the L distance measurement into the vertical dimension rather than the horizontal plane. The distance L is maintained from the metal contact hole at the top surface down to the polysilicon gate in the underlying layer, preserving the electrostatic protection capability while allowing compact horizontal spacing between fingers that reduces overall device area.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The structure employs a nested configuration where multiple source-drain-channel finger units are stacked and interlaced vertically. Each finger unit contains its own L distance for ESD protection, and these units are nested together in a compact arrangement that shares common polysilicon gates and substrate regions, reducing the total area required compared to having separate planar structures for each protection unit.

Inventive Principle:
Principle #7Nested doll (Nesting)

Data Source

PatentUS20160181238A1Electrostatic protective device
Publication Date: 2016.06.23 SHANGHAI HUAHONG GRACE SEMICON MFG CORP
  • US20160181238A1 patent drawing
  • US20160181238A1 patent drawing
  • US20160181238A1 patent drawing

AI summary

The present invention discloses an electrostatic protective device structure, which comprises a CMOS transistor that is disposed entirely above a P-type silicon substrate and arranged into a multi-finger-pattern structure, wherein on the outermost side on both sides of this electrostatic protective device structure is the source region of the MOS transistor, an active region of other drain region or source region in addition to the outermost source region on both sides is arranged in comb teeth pattern and in pairwise intersection, between the active regions of the adjacent drain region or source region is a field oxide region isolation, and on the drain region or source region is disposed a contact hole connecting metal with the active region, wherein the contact hole on the comb-tooth-pattern and pairwise intersected active region is located at the top of the comb-tooth-pattern active region, i.e. close to a side of the field oxide region isolation far away from the polysilicon gate. The present invention, mainly applied to electrostatic protection of a low-voltage MOS, is capable of not only improving its electrostatic protection capability effectively but also minimizing the occupied area of the protective device, and able to be used as both an electrostatic protective device and a power device.