Multi-finger Gate Nonvolatile Memory Cell Design
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Solution Overview
Problem
Current nonvolatile memory devices face inefficiencies in programming speed and reliability due to the degradation of the dielectric layer caused by the injection of hot electrons and holes during programming and erasing operations, leading to a shorter device lifetime.
Innovation Solution
The design incorporates a floating gate with two fingers of different widths, where hot electrons are injected during programming and hot holes during erasing, with doped regions laterally displaced from the floating gate fingers to minimize device degradation and enhance programming efficiency by increasing the generation rate of hot electrons and improving the coupling ratio.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a typical gate length of 0.55 μm is used, then the device structure is simple, but programming is inefficient resulting in slow programming speed
Solution Approach 1:
The floating gate is divided into multiple fingers (first floating gate finger, second floating gate finger, etc.) with different widths. This segmentation allows each finger to serve specific functions: narrower fingers for efficient hot electron injection during programming, and wider fingers for effective hot hole injection during erasing, thereby improving programming speed without excessive complexity
Solution Approach 2:
Different regions of the floating gate are given different widths to optimize local functions. The first floating gate finger has a narrower width optimized for programming efficiency, while the second floating gate finger has a wider width optimized for erasing efficiency. This local differentiation resolves the contradiction by making each region specialized rather than uniform
2Reliability
If hot electrons are injected to the gate electrode during programming, then programming function is achieved, but dielectric layer degradation occurs leading to shorter device lifetime
Solution Approach 1:
The floating gate is segmented into multiple fingers that separate the injection locations of hot electrons and hot holes. Hot electrons are injected primarily to the first floating gate finger during programming, while hot holes are injected to the second floating gate finger during erasing. This spatial separation reduces cumulative degradation at any single location, extending device lifetime
Solution Approach 2:
The patent converts the harmful effect of hot carrier injection into a beneficial outcome by using the different injection locations to advantage. The controlled injection of hot electrons and hot holes to different floating gate fingers not only achieves programming and erasing functions but also distributes the degradation stress, ultimately improving reliability
3Reliability
If hot holes are injected to the gate electrode during erasing, then erasing function is achieved, but dielectric layer degradation occurs leading to shorter device lifetime
Solution Approach 1:
The floating gate structure segments the erasing function to specific wider fingers that are optimized for hot hole injection. This segmentation concentrates the erasing action and associated degradation to specific regions, while other regions remain relatively preserved, extending overall device lifetime
Solution Approach 2:
The patent transforms the potentially harmful hot hole injection during erasing into a beneficial distributed stress pattern. By designing wider floating gate fingers specifically for hot hole injection, the degradation is concentrated in controlled areas rather than uniformly distributed, allowing other areas to maintain integrity longer
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in faster programming speed, a larger program/erase window, and improved device reliability by minimizing degradation and ensuring hot electrons and holes are injected to different locations, thereby extending the device's lifetime.
Implementation Method 1
injection of hot electrons to an edge portion of the gate electrode through the dielectric layer from the channel region near the drain
Implementation Method 2
injection of hot electrons and holes to the gate electrode during program and erase operations
Implementation Method 3
Electron hole pairs may be generated at the drain region by band to band (BTB) tunneling
Implementation Method 4
The generated holes may be injected into the gate electrode through the dielectric layer from the drain region
Implementation Method 5
The biasing conditions create a strong vertically oriented electric field in a channel region between the source and the drain of the memory transistor resulting in injection of hot electrons
Implementation Method 6
The narrow width of the first floating gate finger results in increased programming efficiency and faster programming speed due to enhanced impact ionization and a higher generation rate of hot electrons
Data Source
AI summary
A nonvolatile memory device is provided. The device comprises a floating gate having a first finger and a second finger and an active region below the floating gate fingers. A first doped region is in the active region laterally displaced from the first floating gate finger on a first side. A second doped region is in the active region laterally displaced from the first floating gate finger on a second side. A third doped region is in the active region laterally displaced from the second floating gate finger and the second doped region.