Multi-Finger Transistor Layout With Air Gaps for Lower Gate-Drain Capacitance

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Solution Overview

Problem

The demand for RF front-end modules in 5G communication networks, particularly for power amplifiers and low noise amplifiers operating in millimeter wave frequency bands, poses challenges in miniaturization and high-frequency operation. Existing technologies face issues with increased gate resistance, reduced maximum oscillation frequency, and breakdown voltage, necessitating a reduction in parasitic capacitance between the gate and drain.

Innovation Solution

A multi-finger transistor structure with an asymmetric source/drain design and air gap structures is introduced to reduce parasitic capacitance. The structure includes a gate structure with multiple gate parts and connecting parts forming a meander shape, with sources and drains positioned asymmetrically relative to the gate parts. Air gaps are formed in the dielectric layer between the drains and the gate parts to further reduce capacitance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Length of moving object

If miniaturization is implemented to improve cut-off frequency, then device size is reduced and cut-off frequency is improved, but gate resistance increases and maximum oscillation frequency and breakdown voltage are reduced

Engineering Contradiction:
Improvedevice sizeVSAvoidbreakdown voltage
Core Design Contradiction:
Length of moving objectVSReliability

Solution Approach 1:

The transistor gate is divided into multiple fingers (e.g., five fingers) arranged in a multi-finger configuration. This segmentation reduces the gate resistance by providing multiple parallel conduction paths while maintaining a compact overall device footprint, thus addressing the contradiction between miniaturization and gate resistance reduction.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces air gaps between adjacent gate fingers in the vertical dimension, creating isolation regions that reduce parasitic capacitance between gates and drains. This dimensional approach allows the device to maintain small footprint while improving high-frequency performance and breakdown voltage through reduced capacitive coupling.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Length of moving object

If miniaturization is implemented to improve cut-off frequency, then device size is reduced and cut-off frequency is improved, but maximum oscillation frequency is reduced

Engineering Contradiction:
Improvedevice sizeVSAvoidmaximum oscillation frequency
Core Design Contradiction:
Length of moving objectVSSpeed

Solution Approach 1:

Air gaps are formed between adjacent gate fingers in the vertical dimension to reduce parasitic capacitance between gate and drain. This reduction in parasitic capacitance directly improves the maximum oscillation frequency by decreasing the capacitive load that limits high-frequency operation, while the device maintains its miniaturized footprint.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

3Ease of manufacture

If conventional symmetric source/drain design is used, then manufacturing is simpler, but parasitic capacitance between gate and drain is higher

Engineering Contradiction:
Improvemanufacturing simplicityVSAvoidparasitic capacitance
Core Design Contradiction:
Ease of manufactureVSObject-generated harmful factors

Solution Approach 1:

The patent employs asymmetric source/drain design where the drain region is extended further away from the gate compared to the source region. This asymmetric configuration reduces the parasitic capacitance between gate and drain by increasing the effective distance between these high-potential regions, while the manufacturing process remains compatible with standard CMOS fabrication techniques.

Inventive Principle:
Principle #4Asymmetry

Solution Approach 2:

Air gaps are introduced between adjacent gate fingers in the vertical dimension to reduce parasitic capacitance. This approach directly addresses the harmful capacitive coupling without complicating the manufacturing process, as the air gaps are formed through standard spacer and etch processes.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Data Source

PatentUS20250072092A1Multi-finger transistor structure and method of manufacturing the same
Publication Date: 2025.02.27 UNITED MICROELECTRONICS CORP
  • US20250072092A1 patent drawing
  • US20250072092A1 patent drawing
  • US20250072092A1 patent drawing

AI summary

A method of manufacturing a multi-finger transistor structure is provided in the present invention, including forming shallow trench isolations in a substrate to define multiple active areas, forming a gate structure on the substrate, wherein the gate structure includes multiple gate parts and multiple connecting parts, and each gate part traverses over one of the active area, and each connecting part alternatively connect one end and the other end of two adjacent gate parts, so as to form meander gate structure.