Asymmetric Multi-Finger Transistor Layout With Air Gaps for Lower Cgd
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Solution Overview
Problem
The demand for RF-SOI substrates in 5G communication technology requires miniaturization and high-frequency operation, which increases gate resistance and reduces breakdown voltage, necessitating a reduction in parasitic capacitance between the gate and drain to maintain device performance.
Innovation Solution
A multi-finger transistor structure with asymmetric source/drain design and air gaps in the dielectric layer, combined with shallow trench isolations, to reduce parasitic capacitance and increase breakdown voltage, while saving one photomask in the formation of lightly-doped drains.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If miniaturization is implemented to improve cut-off frequency, then device size is reduced and cut-off frequency is improved, but gate resistance increases and breakdown voltage is reduced
Solution Approach 1:
The transistor gate is divided into multiple fingers (e.g., five fingers) arranged in parallel. This segmentation reduces the gate resistance by providing multiple current paths while maintaining a compact overall device footprint, thus improving cut-off frequency without sacrificing breakdown voltage
Solution Approach 2:
The patent introduces air gaps in the vertical dimension between the gate and drain regions. This three-dimensional structural modification reduces the parasitic capacitance (Cgd) by increasing the separation distance, thereby maintaining breakdown voltage and high-frequency performance in miniaturized devices
2Speed
If miniaturization is implemented to improve cut-off frequency, then device size is reduced, but parasitic capacitance between gate and drain increases
Solution Approach 1:
Air gaps are introduced in the vertical dimension between the gate and drain regions. This three-dimensional structural modification reduces the parasitic capacitance (Cgd) by increasing the separation distance, thereby maintaining high-frequency performance in miniaturized devices
Solution Approach 2:
An air gap (vacuum/void space) is introduced as an intermediary between the gate and drain regions. This intermediary structure reduces the parasitic capacitance by providing electrical isolation while maintaining compact device dimensions
3Reliability
If asymmetric source/drain design with air gaps is implemented, then parasitic capacitance is reduced and breakdown voltage is increased, but device structure becomes more complex
Solution Approach 1:
The source and drain regions are designed with asymmetric dimensions and positioning relative to the gate fingers. The drain region is positioned farther from the gate than the source region, and air gaps are selectively introduced in the drain-gate region. This asymmetric design reduces parasitic capacitance and enhances breakdown voltage while maintaining manufacturability through standard photolithography processes
Data Source
AI summary
A multi-finger transistor structure is provided in the present invention, including multiple active areas, a gate structure consisting of multiple gate parts and connecting parts, wherein each gate part crosses over one of the active areas and each connecting part alternatively connects one end and the other end of the gate parts so as to form a meander gate structure, and multiple sources and drains, wherein one source and one drain are set between two adjacent gate parts, and each gate parts is accompanied by one source and one drain at two sides respectively, and the distance between the drain and the gate part is larger than the distance between the source and the gate part, so that the source and the drain are asymmetric with respect to the corresponding gate part, and air gaps are formed in the dielectric layer between each drain and the corresponding gate part.